hi6220.dtsi (998605407249dd278aef28c1cc2ce00f90c09eaa) hi6220.dtsi (c2aad93200fa2dbbc6c48632e619494080d64796)
1/*
2 * dts file for Hisilicon Hi6220 SoC
3 *
4 * Copyright (C) 2015, Hisilicon Ltd.
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/clock/hi6220-clock.h>

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261
262 uart1: uart@f7111000 {
263 compatible = "arm,pl011", "arm,primecell";
264 reg = <0x0 0xf7111000 0x0 0x1000>;
265 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
267 <&sys_ctrl HI6220_UART1_PCLK>;
268 clock-names = "uartclk", "apb_pclk";
1/*
2 * dts file for Hisilicon Hi6220 SoC
3 *
4 * Copyright (C) 2015, Hisilicon Ltd.
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/clock/hi6220-clock.h>

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261
262 uart1: uart@f7111000 {
263 compatible = "arm,pl011", "arm,primecell";
264 reg = <0x0 0xf7111000 0x0 0x1000>;
265 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
267 <&sys_ctrl HI6220_UART1_PCLK>;
268 clock-names = "uartclk", "apb_pclk";
269 pinctrl-names = "default";
270 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func1 &uart1_cfg_func2>;
269 status = "disabled";
270 };
271
272 uart2: uart@f7112000 {
273 compatible = "arm,pl011", "arm,primecell";
274 reg = <0x0 0xf7112000 0x0 0x1000>;
275 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
277 <&sys_ctrl HI6220_UART2_PCLK>;
278 clock-names = "uartclk", "apb_pclk";
271 status = "disabled";
272 };
273
274 uart2: uart@f7112000 {
275 compatible = "arm,pl011", "arm,primecell";
276 reg = <0x0 0xf7112000 0x0 0x1000>;
277 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
279 <&sys_ctrl HI6220_UART2_PCLK>;
280 clock-names = "uartclk", "apb_pclk";
281 pinctrl-names = "default";
282 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
279 status = "disabled";
280 };
281
282 uart3: uart@f7113000 {
283 compatible = "arm,pl011", "arm,primecell";
284 reg = <0x0 0xf7113000 0x0 0x1000>;
285 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
287 <&sys_ctrl HI6220_UART3_PCLK>;
288 clock-names = "uartclk", "apb_pclk";
283 status = "disabled";
284 };
285
286 uart3: uart@f7113000 {
287 compatible = "arm,pl011", "arm,primecell";
288 reg = <0x0 0xf7113000 0x0 0x1000>;
289 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
291 <&sys_ctrl HI6220_UART3_PCLK>;
292 clock-names = "uartclk", "apb_pclk";
293 pinctrl-names = "default";
294 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
295 status = "disabled";
289 };
290
291 uart4: uart@f7114000 {
292 compatible = "arm,pl011", "arm,primecell";
293 reg = <0x0 0xf7114000 0x0 0x1000>;
294 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
296 <&sys_ctrl HI6220_UART4_PCLK>;
297 clock-names = "uartclk", "apb_pclk";
296 };
297
298 uart4: uart@f7114000 {
299 compatible = "arm,pl011", "arm,primecell";
300 reg = <0x0 0xf7114000 0x0 0x1000>;
301 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
303 <&sys_ctrl HI6220_UART4_PCLK>;
304 clock-names = "uartclk", "apb_pclk";
305 pinctrl-names = "default";
306 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
298 status = "disabled";
299 };
300
301 dual_timer0: timer@f8008000 {
302 compatible = "arm,sp804", "arm,primecell";
303 reg = <0x0 0xf8008000 0x0 0x1000>;
304 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

--- 410 unchanged lines hidden --- 		307 status = "disabled";
308 };
309
310 dual_timer0: timer@f8008000 {
311 compatible = "arm,sp804", "arm,primecell";
312 reg = <0x0 0xf8008000 0x0 0x1000>;
313 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;

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