imx8mq.dtsi (f8d1fc05e2881fe3e466b212af7a2b67c2d88f8d) imx8mq.dtsi (0bcc4bf063b2843a2e9897c0477f7ad4609ae06d)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7#include <dt-bindings/clock/imx8mq-clock.h>
8#include <dt-bindings/power/imx8mq-power.h>

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549 <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
550 <&clk IMX8MQ_VIDEO_PLL1>;
551 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
552 <&clk IMX8MQ_VIDEO_PLL1>,
553 <&clk IMX8MQ_VIDEO_PLL1_OUT>;
554 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
555 status = "disabled";
556
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7#include <dt-bindings/clock/imx8mq-clock.h>
8#include <dt-bindings/power/imx8mq-power.h>

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549 <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
550 <&clk IMX8MQ_VIDEO_PLL1>;
551 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
552 <&clk IMX8MQ_VIDEO_PLL1>,
553 <&clk IMX8MQ_VIDEO_PLL1_OUT>;
554 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
555 status = "disabled";
556
557 port {
557 port@0 {
558 lcdif_mipi_dsi: endpoint {
559 remote-endpoint = <&mipi_dsi_lcdif_in>;
560 };
561 };
562 };
563
564 iomuxc: pinctrl@30330000 {
565 compatible = "fsl,imx8mq-iomuxc";

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1146 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
1147 interconnect-names = "dram";
1148 status = "disabled";
1149
1150 ports {
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1153
558 lcdif_mipi_dsi: endpoint {
559 remote-endpoint = <&mipi_dsi_lcdif_in>;
560 };
561 };
562 };
563
564 iomuxc: pinctrl@30330000 {
565 compatible = "fsl,imx8mq-iomuxc";

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1146 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
1147 interconnect-names = "dram";
1148 status = "disabled";
1149
1150 ports {
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1153
1154 port@1 {
1155 reg = <1>;
1154 port@0 {
1155 reg = <0>;
1156
1157 csi1_mipi_ep: endpoint {
1158 remote-endpoint = <&csi1_ep>;
1159 };
1160 };
1161 };
1162 };
1163

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1198 interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
1199 interconnect-names = "dram";
1200 status = "disabled";
1201
1202 ports {
1203 #address-cells = <1>;
1204 #size-cells = <0>;
1205
1156
1157 csi1_mipi_ep: endpoint {
1158 remote-endpoint = <&csi1_ep>;
1159 };
1160 };
1161 };
1162 };
1163

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1198 interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>;
1199 interconnect-names = "dram";
1200 status = "disabled";
1201
1202 ports {
1203 #address-cells = <1>;
1204 #size-cells = <0>;
1205
1206 port@1 {
1207 reg = <1>;
1206 port@0 {
1207 reg = <0>;
1208
1209 csi2_mipi_ep: endpoint {
1210 remote-endpoint = <&csi2_ep>;
1211 };
1212 };
1213 };
1214 };
1215

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1574 ddrc: memory-controller@3d400000 {
1575 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1576 reg = <0x3d400000 0x400000>;
1577 clock-names = "core", "pll", "alt", "apb";
1578 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
1579 <&clk IMX8MQ_DRAM_PLL_OUT>,
1580 <&clk IMX8MQ_CLK_DRAM_ALT>,
1581 <&clk IMX8MQ_CLK_DRAM_APB>;
1208
1209 csi2_mipi_ep: endpoint {
1210 remote-endpoint = <&csi2_ep>;
1211 };
1212 };
1213 };
1214 };
1215

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1574 ddrc: memory-controller@3d400000 {
1575 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1576 reg = <0x3d400000 0x400000>;
1577 clock-names = "core", "pll", "alt", "apb";
1578 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
1579 <&clk IMX8MQ_DRAM_PLL_OUT>,
1580 <&clk IMX8MQ_CLK_DRAM_ALT>,
1581 <&clk IMX8MQ_CLK_DRAM_APB>;
1582 status = "disabled";
1582 };
1583
1584 ddr-pmu@3d800000 {
1585 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1586 reg = <0x3d800000 0x400000>;
1587 interrupt-parent = <&gic>;
1588 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1589 };
1590 };
1591};
1583 };
1584
1585 ddr-pmu@3d800000 {
1586 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1587 reg = <0x3d800000 0x400000>;
1588 interrupt-parent = <&gic>;
1589 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1590 };
1591 };
1592};