imx8mq.dtsi (614d88460f28cc0e73268ab89c770a909d7004a5) imx8mq.dtsi (12fa1078efc871604d62e992cb8a038421b82096)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7#include <dt-bindings/clock/imx8mq-clock.h>
8#include <dt-bindings/power/imx8mq-power.h>

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537
538 mux: mux-controller {
539 compatible = "mmio-mux";
540 #mux-control-cells = <1>;
541 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
542 };
543 };
544
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7#include <dt-bindings/clock/imx8mq-clock.h>
8#include <dt-bindings/power/imx8mq-power.h>

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537
538 mux: mux-controller {
539 compatible = "mmio-mux";
540 #mux-control-cells = <1>;
541 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
542 };
543 };
544
545 ocotp: ocotp-ctrl@30350000 {
545 ocotp: efuse@30350000 {
546 compatible = "fsl,imx8mq-ocotp", "syscon";
547 reg = <0x30350000 0x10000>;
548 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
549 #address-cells = <1>;
550 #size-cells = <1>;
551
552 cpu_speed_grade: speed-grade@10 {
553 reg = <0x10 4>;

--- 711 unchanged lines hidden --- 		546 compatible = "fsl,imx8mq-ocotp", "syscon";
547 reg = <0x30350000 0x10000>;
548 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
549 #address-cells = <1>;
550 #size-cells = <1>;
551
552 cpu_speed_grade: speed-grade@10 {
553 reg = <0x10 4>;

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