imx8mn.dtsi (966a9b49033b472dcfb453abdc34bca7df17adce) imx8mn.dtsi (5468e93b5b1083eaa729f98e59da18c85d9c4126)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/power/imx8mn-power.h>
8#include <dt-bindings/reset/imx8mq-reset.h>

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1097 #dma-cells = <1>;
1098 dma-channels = <4>;
1099 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1100 };
1101
1102 gpmi: nand-controller@33002000 {
1103 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1104 #address-cells = <1>;
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/power/imx8mn-power.h>
8#include <dt-bindings/reset/imx8mq-reset.h>

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1097 #dma-cells = <1>;
1098 dma-channels = <4>;
1099 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1100 };
1101
1102 gpmi: nand-controller@33002000 {
1103 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1104 #address-cells = <1>;
1105 #size-cells = <1>;
1105 #size-cells = <0>;
1106 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1107 reg-names = "gpmi-nand", "bch";
1108 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1109 interrupt-names = "bch";
1110 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
1111 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1112 clock-names = "gpmi_io", "gpmi_bch_apb";
1113 dmas = <&dma_apbh 0>;

--- 66 unchanged lines hidden --- 		1106 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1107 reg-names = "gpmi-nand", "bch";
1108 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1109 interrupt-names = "bch";
1110 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
1111 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1112 clock-names = "gpmi_io", "gpmi_bch_apb";
1113 dmas = <&dma_apbh 0>;

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