imx8mn.dtsi (942e6f8a8314e5550e254519dfba4ccd5170421d) imx8mn.dtsi (0f93eb28ff3a348818509aac7850a8f6df114a3f)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

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344
345 cpu_speed_grade: speed-grade@10 {
346 reg = <0x10 4>;
347 };
348 };
349
350 anatop: anatop@30360000 {
351 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

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344
345 cpu_speed_grade: speed-grade@10 {
346 reg = <0x10 4>;
347 };
348 };
349
350 anatop: anatop@30360000 {
351 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
352 "syscon", "simple-bus";
352 "syscon";
353 reg = <0x30360000 0x10000>;
354 };
355
356 snvs: snvs@30370000 {
357 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
358 reg = <0x30370000 0x10000>;
359
360 snvs_rtc: snvs-rtc-lp {

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354 };
355
356 snvs: snvs@30370000 {
357 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
358 reg = <0x30370000 0x10000>;
359
360 snvs_rtc: snvs-rtc-lp {

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