imx8mn.dtsi (42ef961b247f340f365b096e25983b4ee256f3ab) imx8mn.dtsi (53458f86683bee0551c87db4022e6ccc3ab8c868)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

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375 clk: clock-controller@30380000 {
376 compatible = "fsl,imx8mn-ccm";
377 reg = <0x30380000 0x10000>;
378 #clock-cells = <1>;
379 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
380 <&clk_ext3>, <&clk_ext4>;
381 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
382 "clk_ext3", "clk_ext4";
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

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375 clk: clock-controller@30380000 {
376 compatible = "fsl,imx8mn-ccm";
377 reg = <0x30380000 0x10000>;
378 #clock-cells = <1>;
379 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
380 <&clk_ext3>, <&clk_ext4>;
381 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
382 "clk_ext3", "clk_ext4";
383 assigned-clocks = <&clk IMX8MN_CLK_NOC>,
384 <&clk IMX8MN_CLK_AUDIO_AHB>,
385 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
386 <&clk IMX8MN_SYS_PLL3>;
387 assigned-clock-parents = <&clk IMX8MN_SYS_PLL3_OUT>,
388 <&clk IMX8MN_SYS_PLL1_800M>;
389 assigned-clock-rates = <0>,
390 <400000000>,
391 <400000000>,
392 <600000000>;
383 };
384
385 src: reset-controller@30390000 {
386 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
387 reg = <0x30390000 0x10000>;
388 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
389 #reset-cells = <1>;
390 };

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393 };
394
395 src: reset-controller@30390000 {
396 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
397 reg = <0x30390000 0x10000>;
398 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
399 #reset-cells = <1>;
400 };

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