imx8mn.dtsi (41d91ec3de8a90167159275bde7ed65768723556) imx8mn.dtsi (15ddc3e17aec0de4c69d595b873e184432b9791d)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

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713 status = "disabled";
714 };
715
716 sdma1: dma-controller@30bd0000 {
717 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
718 reg = <0x30bd0000 0x10000>;
719 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

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713 status = "disabled";
714 };
715
716 sdma1: dma-controller@30bd0000 {
717 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
718 reg = <0x30bd0000 0x10000>;
719 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
720 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
721 <&clk IMX8MN_CLK_SDMA1_ROOT>;
721 <&clk IMX8MN_CLK_AHB>;
722 clock-names = "ipg", "ahb";
723 #dma-cells = <3>;
724 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
725 };
726
727 fec1: ethernet@30be0000 {
728 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
729 reg = <0x30be0000 0x10000>;

--- 145 unchanged lines hidden --- 		722 clock-names = "ipg", "ahb";
723 #dma-cells = <3>;
724 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
725 };
726
727 fec1: ethernet@30be0000 {
728 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
729 reg = <0x30be0000 0x10000>;

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