imx8mn.dtsi (2d8e0747e5ad10139b26e9f40c050089147f2f98) imx8mn.dtsi (ea65aba85e8143c3854b66f40be09b6b79215006)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

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38 spi1 = &ecspi2;
39 spi2 = &ecspi3;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mn-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

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38 spi1 = &ecspi2;
39 spi2 = &ecspi3;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 idle-states {
47 entry-method = "psci";
48
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
56 };
57 };
58
59 A53_0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0>;
63 clock-latency = <61036>;
64 clocks = <&clk IMX8MN_CLK_ARM>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
46 A53_0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a53";
49 reg = <0x0>;
50 clock-latency = <61036>;
51 clocks = <&clk IMX8MN_CLK_ARM>;
52 enable-method = "psci";
53 next-level-cache = <&A53_L2>;
54 operating-points-v2 = <&a53_opp_table>;
55 nvmem-cells = <&cpu_speed_grade>;
56 nvmem-cell-names = "speed_grade";
70 cpu-idle-states = <&cpu_pd_wait>;
71 };
72
73 A53_1: cpu@1 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a53";
76 reg = <0x1>;
77 clock-latency = <61036>;
78 clocks = <&clk IMX8MN_CLK_ARM>;
79 enable-method = "psci";
80 next-level-cache = <&A53_L2>;
81 operating-points-v2 = <&a53_opp_table>;
57 };
58
59 A53_1: cpu@1 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x1>;
63 clock-latency = <61036>;
64 clocks = <&clk IMX8MN_CLK_ARM>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
67 operating-points-v2 = <&a53_opp_table>;
82 cpu-idle-states = <&cpu_pd_wait>;
83 };
84
85 A53_2: cpu@2 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a53";
88 reg = <0x2>;
89 clock-latency = <61036>;
90 clocks = <&clk IMX8MN_CLK_ARM>;
91 enable-method = "psci";
92 next-level-cache = <&A53_L2>;
93 operating-points-v2 = <&a53_opp_table>;
68 };
69
70 A53_2: cpu@2 {
71 device_type = "cpu";
72 compatible = "arm,cortex-a53";
73 reg = <0x2>;
74 clock-latency = <61036>;
75 clocks = <&clk IMX8MN_CLK_ARM>;
76 enable-method = "psci";
77 next-level-cache = <&A53_L2>;
78 operating-points-v2 = <&a53_opp_table>;
94 cpu-idle-states = <&cpu_pd_wait>;
95 };
96
97 A53_3: cpu@3 {
98 device_type = "cpu";
99 compatible = "arm,cortex-a53";
100 reg = <0x3>;
101 clock-latency = <61036>;
102 clocks = <&clk IMX8MN_CLK_ARM>;
103 enable-method = "psci";
104 next-level-cache = <&A53_L2>;
105 operating-points-v2 = <&a53_opp_table>;
79 };
80
81 A53_3: cpu@3 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a53";
84 reg = <0x3>;
85 clock-latency = <61036>;
86 clocks = <&clk IMX8MN_CLK_ARM>;
87 enable-method = "psci";
88 next-level-cache = <&A53_L2>;
89 operating-points-v2 = <&a53_opp_table>;
106 cpu-idle-states = <&cpu_pd_wait>;
107 };
108
109 A53_L2: l2-cache0 {
110 compatible = "cache";
111 };
112 };
113
114 a53_opp_table: opp-table {

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332 };
333
334 gpr: iomuxc-gpr@30340000 {
335 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
336 reg = <0x30340000 0x10000>;
337 };
338
339 ocotp: ocotp-ctrl@30350000 {
90 };
91
92 A53_L2: l2-cache0 {
93 compatible = "cache";
94 };
95 };
96
97 a53_opp_table: opp-table {

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315 };
316
317 gpr: iomuxc-gpr@30340000 {
318 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
319 reg = <0x30340000 0x10000>;
320 };
321
322 ocotp: ocotp-ctrl@30350000 {
340 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
323 compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
341 reg = <0x30350000 0x10000>;
342 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
343 #address-cells = <1>;
344 #size-cells = <1>;
345
346 cpu_speed_grade: speed-grade@10 {
347 reg = <0x10 4>;
348 };

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383 #clock-cells = <1>;
384 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
385 <&clk_ext3>, <&clk_ext4>;
386 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
387 "clk_ext3", "clk_ext4";
388 };
389
390 src: reset-controller@30390000 {
324 reg = <0x30350000 0x10000>;
325 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
326 #address-cells = <1>;
327 #size-cells = <1>;
328
329 cpu_speed_grade: speed-grade@10 {
330 reg = <0x10 4>;
331 };

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366 #clock-cells = <1>;
367 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
368 <&clk_ext3>, <&clk_ext4>;
369 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
370 "clk_ext3", "clk_ext4";
371 };
372
373 src: reset-controller@30390000 {
391 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
374 compatible = "fsl,imx8mn-src", "syscon";
392 reg = <0x30390000 0x10000>;
393 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
394 #reset-cells = <1>;
395 };
396 };
397
398 aips2: bus@30400000 {
399 compatible = "fsl,aips-bus", "simple-bus";

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440 reg = <0x30690000 0x10000>;
441 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
443 <&clk IMX8MN_CLK_PWM4_ROOT>;
444 clock-names = "ipg", "per";
445 #pwm-cells = <2>;
446 status = "disabled";
447 };
375 reg = <0x30390000 0x10000>;
376 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
377 #reset-cells = <1>;
378 };
379 };
380
381 aips2: bus@30400000 {
382 compatible = "fsl,aips-bus", "simple-bus";

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423 reg = <0x30690000 0x10000>;
424 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
426 <&clk IMX8MN_CLK_PWM4_ROOT>;
427 clock-names = "ipg", "per";
428 #pwm-cells = <2>;
429 status = "disabled";
430 };
448
449 system_counter: timer@306a0000 {
450 compatible = "nxp,sysctr-timer";
451 reg = <0x306a0000 0x20000>;
452 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&osc_24m>;
454 clock-names = "per";
455 };
456 };
457
458 aips3: bus@30800000 {
459 compatible = "fsl,aips-bus", "simple-bus";
460 reg = <0x30800000 0x400000>;
461 #address-cells = <1>;
462 #size-cells = <1>;
463 ranges;

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589 dma-names = "rx", "tx";
590 status = "disabled";
591 };
592
593 usdhc1: mmc@30b40000 {
594 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
595 reg = <0x30b40000 0x10000>;
596 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
431 };
432
433 aips3: bus@30800000 {
434 compatible = "fsl,aips-bus", "simple-bus";
435 reg = <0x30800000 0x400000>;
436 #address-cells = <1>;
437 #size-cells = <1>;
438 ranges;

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564 dma-names = "rx", "tx";
565 status = "disabled";
566 };
567
568 usdhc1: mmc@30b40000 {
569 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
570 reg = <0x30b40000 0x10000>;
571 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
597 clocks = <&clk IMX8MN_CLK_DUMMY>,
572 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
598 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
599 <&clk IMX8MN_CLK_USDHC1_ROOT>;
600 clock-names = "ipg", "ahb", "per";
601 assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
602 assigned-clock-rates = <400000000>;
603 fsl,tuning-start-tap = <20>;
604 fsl,tuning-step= <2>;
605 bus-width = <4>;
606 status = "disabled";
607 };
608
609 usdhc2: mmc@30b50000 {
610 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
611 reg = <0x30b50000 0x10000>;
612 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
573 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
574 <&clk IMX8MN_CLK_USDHC1_ROOT>;
575 clock-names = "ipg", "ahb", "per";
576 assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
577 assigned-clock-rates = <400000000>;
578 fsl,tuning-start-tap = <20>;
579 fsl,tuning-step= <2>;
580 bus-width = <4>;
581 status = "disabled";
582 };
583
584 usdhc2: mmc@30b50000 {
585 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
586 reg = <0x30b50000 0x10000>;
587 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&clk IMX8MN_CLK_DUMMY>,
588 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
614 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
615 <&clk IMX8MN_CLK_USDHC2_ROOT>;
616 clock-names = "ipg", "ahb", "per";
617 fsl,tuning-start-tap = <20>;
618 fsl,tuning-step= <2>;
619 bus-width = <4>;
620 status = "disabled";
621 };
622
623 usdhc3: mmc@30b60000 {
624 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
625 reg = <0x30b60000 0x10000>;
626 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
589 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
590 <&clk IMX8MN_CLK_USDHC2_ROOT>;
591 clock-names = "ipg", "ahb", "per";
592 fsl,tuning-start-tap = <20>;
593 fsl,tuning-step= <2>;
594 bus-width = <4>;
595 status = "disabled";
596 };
597
598 usdhc3: mmc@30b60000 {
599 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
600 reg = <0x30b60000 0x10000>;
601 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&clk IMX8MN_CLK_DUMMY>,
602 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
628 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
629 <&clk IMX8MN_CLK_USDHC3_ROOT>;
630 clock-names = "ipg", "ahb", "per";
631 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
632 assigned-clock-rates = <400000000>;
633 fsl,tuning-start-tap = <20>;
634 fsl,tuning-step= <2>;
635 bus-width = <4>;

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758 gic: interrupt-controller@38800000 {
759 compatible = "arm,gic-v3";
760 reg = <0x38800000 0x10000>,
761 <0x38880000 0xc0000>;
762 #interrupt-cells = <3>;
763 interrupt-controller;
764 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
765 };
603 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
604 <&clk IMX8MN_CLK_USDHC3_ROOT>;
605 clock-names = "ipg", "ahb", "per";
606 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
607 assigned-clock-rates = <400000000>;
608 fsl,tuning-start-tap = <20>;
609 fsl,tuning-step= <2>;
610 bus-width = <4>;

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733 gic: interrupt-controller@38800000 {
734 compatible = "arm,gic-v3";
735 reg = <0x38800000 0x10000>,
736 <0x38880000 0xc0000>;
737 #interrupt-cells = <3>;
738 interrupt-controller;
739 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
740 };
766
767 ddr-pmu@3d800000 {
768 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
769 reg = <0x3d800000 0x400000>;
770 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
771 };
772 };
773
774 usbphynop1: usbphynop1 {
775 compatible = "usb-nop-xceiv";
776 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
777 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
778 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
779 clock-names = "main_clk";
780 };
781
782 usbphynop2: usbphynop2 {
783 compatible = "usb-nop-xceiv";
784 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
785 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
786 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
787 clock-names = "main_clk";
788 };
789};
741 };
742
743 usbphynop1: usbphynop1 {
744 compatible = "usb-nop-xceiv";
745 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
746 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
747 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
748 clock-names = "main_clk";
749 };
750
751 usbphynop2: usbphynop2 {
752 compatible = "usb-nop-xceiv";
753 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
754 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
755 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
756 clock-names = "main_clk";
757 };
758};