imx8mm.dtsi (ca31fef11dc83e672415d5925a134749761329bd) imx8mm.dtsi (a758dee8ac50cdabc1229ca82bc7472752a51e1d)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mm-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

--- 906 unchanged lines hidden (view full) ---

915 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
916 <&clk IMX8MM_CLK_AHB>;
917 clock-names = "ipg", "ahb";
918 #dma-cells = <3>;
919 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
920 };
921
922 fec1: ethernet@30be0000 {
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mm-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

--- 906 unchanged lines hidden (view full) ---

915 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
916 <&clk IMX8MM_CLK_AHB>;
917 clock-names = "ipg", "ahb";
918 #dma-cells = <3>;
919 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
920 };
921
922 fec1: ethernet@30be0000 {
923 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
923 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
924 reg = <0x30be0000 0x10000>;
925 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
930 <&clk IMX8MM_CLK_ENET1_ROOT>,
931 <&clk IMX8MM_CLK_ENET_TIMER>,

--- 126 unchanged lines hidden --- 		924 reg = <0x30be0000 0x10000>;
925 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
930 <&clk IMX8MM_CLK_ENET1_ROOT>,
931 <&clk IMX8MM_CLK_ENET_TIMER>,

--- 126 unchanged lines hidden ---