imx8mm.dtsi (83ae2848520a91fcb9933e1dbb4d1333f44ee473) imx8mm.dtsi (12fa1078efc871604d62e992cb8a038421b82096)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mm-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

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462 reg = <0x30330000 0x10000>;
463 };
464
465 gpr: iomuxc-gpr@30340000 {
466 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
467 reg = <0x30340000 0x10000>;
468 };
469
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mm-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

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462 reg = <0x30330000 0x10000>;
463 };
464
465 gpr: iomuxc-gpr@30340000 {
466 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
467 reg = <0x30340000 0x10000>;
468 };
469
470 ocotp: ocotp-ctrl@30350000 {
470 ocotp: efuse@30350000 {
471 compatible = "fsl,imx8mm-ocotp", "syscon";
472 reg = <0x30350000 0x10000>;
473 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
474 /* For nvmem subnodes */
475 #address-cells = <1>;
476 #size-cells = <1>;
477
478 cpu_speed_grade: speed-grade@10 {

--- 495 unchanged lines hidden --- 		471 compatible = "fsl,imx8mm-ocotp", "syscon";
472 reg = <0x30350000 0x10000>;
473 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
474 /* For nvmem subnodes */
475 #address-cells = <1>;
476 #size-cells = <1>;
477
478 cpu_speed_grade: speed-grade@10 {

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