imx8mm.dtsi (6f84981772535e670e4e2df051a672af229b6694) imx8mm.dtsi (3c033fb13925898a3fb692b4bdd071250133adda)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mm-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

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491 #interrupt-cells = <2>;
492 gpio-ranges = <&iomuxc 0 119 30>;
493 };
494
495 tmu: tmu@30260000 {
496 compatible = "fsl,imx8mm-tmu";
497 reg = <0x30260000 0x10000>;
498 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mm-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>

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491 #interrupt-cells = <2>;
492 gpio-ranges = <&iomuxc 0 119 30>;
493 };
494
495 tmu: tmu@30260000 {
496 compatible = "fsl,imx8mm-tmu";
497 reg = <0x30260000 0x10000>;
498 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
499 nvmem-cells = <&tmu_calib>;
500 nvmem-cell-names = "calib";
499 #thermal-sensor-cells = <0>;
500 };
501
502 wdog1: watchdog@30280000 {
503 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
504 reg = <0x30280000 0x10000>;
505 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;

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545 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
546 };
547
548 iomuxc: pinctrl@30330000 {
549 compatible = "fsl,imx8mm-iomuxc";
550 reg = <0x30330000 0x10000>;
551 };
552
501 #thermal-sensor-cells = <0>;
502 };
503
504 wdog1: watchdog@30280000 {
505 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
506 reg = <0x30280000 0x10000>;
507 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;

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547 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
548 };
549
550 iomuxc: pinctrl@30330000 {
551 compatible = "fsl,imx8mm-iomuxc";
552 reg = <0x30330000 0x10000>;
553 };
554
553 gpr: iomuxc-gpr@30340000 {
554 compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
555 gpr: syscon@30340000 {
556 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
555 reg = <0x30340000 0x10000>;
556 };
557
558 ocotp: efuse@30350000 {
559 compatible = "fsl,imx8mm-ocotp", "syscon";
560 reg = <0x30350000 0x10000>;
561 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
562 /* For nvmem subnodes */
563 #address-cells = <1>;
564 #size-cells = <1>;
565
557 reg = <0x30340000 0x10000>;
558 };
559
560 ocotp: efuse@30350000 {
561 compatible = "fsl,imx8mm-ocotp", "syscon";
562 reg = <0x30350000 0x10000>;
563 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
564 /* For nvmem subnodes */
565 #address-cells = <1>;
566 #size-cells = <1>;
567
566 imx8mm_uid: unique-id@410 {
568 /*
569 * The register address below maps to the MX8M
570 * Fusemap Description Table entries this way.
571 * Assuming
572 * reg = <ADDR SIZE>;
573 * then
574 * Fuse Address = (ADDR * 4) + 0x400
575 * Note that if SIZE is greater than 4, then
576 * each subsequent fuse is located at offset
577 * +0x10 in Fusemap Description Table (e.g.
578 * reg = <0x4 0x8> describes fuses 0x410 and
579 * 0x420).
580 */
581 imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
567 reg = <0x4 0x8>;
568 };
569
582 reg = <0x4 0x8>;
583 };
584
570 cpu_speed_grade: speed-grade@10 {
585 cpu_speed_grade: speed-grade@10 { /* 0x440 */
571 reg = <0x10 4>;
572 };
573
586 reg = <0x10 4>;
587 };
588
574 fec_mac_address: mac-address@90 {
589 tmu_calib: calib@3c { /* 0x4f0 */
590 reg = <0x3c 4>;
591 };
592
593 fec_mac_address: mac-address@90 { /* 0x640 */
575 reg = <0x90 6>;
576 };
577 };
578
579 anatop: clock-controller@30360000 {
580 compatible = "fsl,imx8mm-anatop";
581 reg = <0x30360000 0x10000>;
582 #clock-cells = <1>;

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1235
1236 dma_apbh: dma-controller@33000000 {
1237 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1238 reg = <0x33000000 0x2000>;
1239 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
594 reg = <0x90 6>;
595 };
596 };
597
598 anatop: clock-controller@30360000 {
599 compatible = "fsl,imx8mm-anatop";
600 reg = <0x30360000 0x10000>;
601 #clock-cells = <1>;

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1254
1255 dma_apbh: dma-controller@33000000 {
1256 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1257 reg = <0x33000000 0x2000>;
1258 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1243 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1244 #dma-cells = <1>;
1245 dma-channels = <4>;
1246 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1247 };
1248
1249 gpmi: nand-controller@33002000 {
1250 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1251 #address-cells = <1>;

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1279 #interrupt-cells = <1>;
1280 interrupt-map-mask = <0 0 0 0x7>;
1281 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1282 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1283 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1284 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1285 fsl,max-link-speed = <2>;
1286 linux,pci-domain = <0>;
1262 #dma-cells = <1>;
1263 dma-channels = <4>;
1264 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1265 };
1266
1267 gpmi: nand-controller@33002000 {
1268 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1269 #address-cells = <1>;

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1297 #interrupt-cells = <1>;
1298 interrupt-map-mask = <0 0 0 0x7>;
1299 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1300 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1301 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1302 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1303 fsl,max-link-speed = <2>;
1304 linux,pci-domain = <0>;
1305 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
1306 <&clk IMX8MM_CLK_PCIE1_PHY>,
1307 <&clk IMX8MM_CLK_PCIE1_AUX>;
1308 clock-names = "pcie", "pcie_bus", "pcie_aux";
1287 power-domains = <&pgc_pcie>;
1288 resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1289 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1290 reset-names = "apps", "turnoff";
1291 phys = <&pcie_phy>;
1292 phy-names = "pcie-phy";
1293 status = "disabled";
1294 };

--- 93 unchanged lines hidden --- 		1309 power-domains = <&pgc_pcie>;
1310 resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1311 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1312 reset-names = "apps", "turnoff";
1313 phys = <&pcie_phy>;
1314 phy-names = "pcie-phy";
1315 status = "disabled";
1316 };

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