Kconfig (5ee9cd065836e5934710ca35653bce7905add20b) Kconfig (93696d8f96a98aa2e1d98bf0003f83b2321090cf)
1# SPDX-License-Identifier: GPL-2.0-only
2config ARM64
3 def_bool y
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_IORT if ACPI

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1063
1064 On an affected Cortex-A510 core, a speculatively executed unprivileged
1065 load might leak data from a privileged level via a cache side channel.
1066
1067 Work around this problem by executing a TLBI before returning to EL0.
1068
1069 If unsure, say Y.
1070
1# SPDX-License-Identifier: GPL-2.0-only
2config ARM64
3 def_bool y
4 select ACPI_APMT if ACPI
5 select ACPI_CCA_REQUIRED if ACPI
6 select ACPI_GENERIC_GSI if ACPI
7 select ACPI_GTDT if ACPI
8 select ACPI_IORT if ACPI

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1063
1064 On an affected Cortex-A510 core, a speculatively executed unprivileged
1065 load might leak data from a privileged level via a cache side channel.
1066
1067 Work around this problem by executing a TLBI before returning to EL0.
1068
1069 If unsure, say Y.
1070
1071config ARM64_WORKAROUND_SPECULATIVE_SSBS
1072 bool
1073
1074config ARM64_ERRATUM_3194386
1075 bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing"
1076 select ARM64_WORKAROUND_SPECULATIVE_SSBS
1077 default y
1078 help
1079 This option adds the workaround for ARM Cortex-X4 erratum 3194386.
1080
1081 On affected cores "MSR SSBS, #0" instructions may not affect
1082 subsequent speculative instructions, which may permit unexepected
1083 speculative store bypassing.
1084
1085 Work around this problem by placing a speculation barrier after
1086 kernel changes to SSBS. The presence of the SSBS special-purpose
1087 register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such
1088 that userspace will use the PR_SPEC_STORE_BYPASS prctl to change
1089 SSBS.
1090
1091 If unsure, say Y.
1092
1093config ARM64_ERRATUM_3312417
1094 bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing"
1095 select ARM64_WORKAROUND_SPECULATIVE_SSBS
1096 default y
1097 help
1098 This option adds the workaround for ARM Neoverse-V3 erratum 3312417.
1099
1100 On affected cores "MSR SSBS, #0" instructions may not affect
1101 subsequent speculative instructions, which may permit unexepected
1102 speculative store bypassing.
1103
1104 Work around this problem by placing a speculation barrier after
1105 kernel changes to SSBS. The presence of the SSBS special-purpose
1106 register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such
1107 that userspace will use the PR_SPEC_STORE_BYPASS prctl to change
1108 SSBS.
1109
1110 If unsure, say Y.
1111
1112
1071config CAVIUM_ERRATUM_22375
1072 bool "Cavium erratum 22375, 24313"
1073 default y
1074 help
1075 Enable workaround for errata 22375 and 24313.
1076
1077 This implements two gicv3-its errata workarounds for ThunderX. Both
1078 with a small impact affecting only ITS table allocation.

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1113config CAVIUM_ERRATUM_22375
1114 bool "Cavium erratum 22375, 24313"
1115 default y
1116 help
1117 Enable workaround for errata 22375 and 24313.
1118
1119 This implements two gicv3-its errata workarounds for ThunderX. Both
1120 with a small impact affecting only ITS table allocation.

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