| proc-v7.S (b73077eb03f510a84b102fb97640e595a958403c) | proc-v7.S (d427958a46af24f75d0017c45eadd172273bbf33) |
|---|---|
| 1/* 2 * linux/arch/arm/mm/proc-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. --- 354 unchanged lines hidden (view full) --- 363 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 364#endif 365 dsb 366#ifdef CONFIG_MMU 367 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 368 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 369 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 370 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) | 1/* 2 * linux/arch/arm/mm/proc-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. --- 354 unchanged lines hidden (view full) --- 363 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 364#endif 365 dsb 366#ifdef CONFIG_MMU 367 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 368 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 369 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 370 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) |
| 371 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 | 371 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) 372 ALT_UP(orr r8, r8, #TTB_FLAGS_UP) 373 mcr p15, 0, r8, c2, c0, 1 @ load TTB1 |
| 372 ldr r5, =PRRR @ PRRR 373 ldr r6, =NMRR @ NMRR 374 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 375 mcr p15, 0, r6, c10, c2, 1 @ write NMRR 376#endif 377 adr r5, v7_crval 378 ldmia r5, {r5, r6} 379#ifdef CONFIG_CPU_ENDIAN_BE8 --- 119 unchanged lines hidden --- | 374 ldr r5, =PRRR @ PRRR 375 ldr r6, =NMRR @ NMRR 376 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 377 mcr p15, 0, r6, c10, c2, 1 @ write NMRR 378#endif 379 adr r5, v7_crval 380 ldmia r5, {r5, r6} 381#ifdef CONFIG_CPU_ENDIAN_BE8 --- 119 unchanged lines hidden --- |