| proc-v7.S (69dbdd819599e2f3b77c172e83af512845bca5ad) | proc-v7.S (247055aa21ffef1c49dd64710d5e94c2aee19b58) |
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| 1/* 2 * linux/arch/arm/mm/proc-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. --- 134 unchanged lines hidden (view full) --- 143 orrne r3, r3, #PTE_EXT_TEX(1) 144 145 tst r1, #L_PTE_WRITE 146 tstne r1, #L_PTE_DIRTY 147 orreq r3, r3, #PTE_EXT_APX 148 149 tst r1, #L_PTE_USER 150 orrne r3, r3, #PTE_EXT_AP1 | 1/* 2 * linux/arch/arm/mm/proc-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. --- 134 unchanged lines hidden (view full) --- 143 orrne r3, r3, #PTE_EXT_TEX(1) 144 145 tst r1, #L_PTE_WRITE 146 tstne r1, #L_PTE_DIRTY 147 orreq r3, r3, #PTE_EXT_APX 148 149 tst r1, #L_PTE_USER 150 orrne r3, r3, #PTE_EXT_AP1 |
| 151#ifdef CONFIG_CPU_USE_DOMAINS 152 @ allow kernel read/write access to read-only user pages |
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| 151 tstne r3, #PTE_EXT_APX 152 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 | 153 tstne r3, #PTE_EXT_APX 154 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 |
| 155#endif |
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| 153 154 tst r1, #L_PTE_EXEC 155 orreq r3, r3, #PTE_EXT_XN 156 157 tst r1, #L_PTE_YOUNG 158 tstne r1, #L_PTE_PRESENT 159 moveq r3, #0 160 --- 107 unchanged lines hidden (view full) --- 268#endif 269 dsb 270#ifdef CONFIG_MMU 271 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 272 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 273 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 274 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 275 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 | 156 157 tst r1, #L_PTE_EXEC 158 orreq r3, r3, #PTE_EXT_XN 159 160 tst r1, #L_PTE_YOUNG 161 tstne r1, #L_PTE_PRESENT 162 moveq r3, #0 163 --- 107 unchanged lines hidden (view full) --- 271#endif 272 dsb 273#ifdef CONFIG_MMU 274 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 275 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 276 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 277 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) 278 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 |
| 276 mov r10, #0x1f @ domains 0, 1 = manager 277 mcr p15, 0, r10, c3, c0, 0 @ load domain access register | |
| 278 /* 279 * Memory region attributes with SCTLR.TRE=1 280 * 281 * n = TEX[0],C,B 282 * TR = PRRR[2n+1:2n] - memory type 283 * IR = NMRR[2n+1:2n] - inner cacheable property 284 * OR = NMRR[2n+17:2n+16] - outer cacheable property 285 * --- 140 unchanged lines hidden --- | 279 /* 280 * Memory region attributes with SCTLR.TRE=1 281 * 282 * n = TEX[0],C,B 283 * TR = PRRR[2n+1:2n] - memory type 284 * IR = NMRR[2n+1:2n] - inner cacheable property 285 * OR = NMRR[2n+17:2n+16] - outer cacheable property 286 * --- 140 unchanged lines hidden --- |