| proc-v6.S (5bdfdfeed5eed599a3ddc455f7c254a209ceae8d) | proc-v6.S (d427958a46af24f75d0017c45eadd172273bbf33) |
|---|---|
| 1/* 2 * linux/arch/arm/mm/proc-v6.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Modified by Catalin Marinas for noMMU support 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 199 unchanged lines hidden (view full) --- 208 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 209 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 210 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 211#ifdef CONFIG_MMU 212 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 213 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 214 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 215 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) | 1/* 2 * linux/arch/arm/mm/proc-v6.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * Modified by Catalin Marinas for noMMU support 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 199 unchanged lines hidden (view full) --- 208 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 209 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 210 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 211#ifdef CONFIG_MMU 212 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 213 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 214 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) 215 ALT_UP(orr r4, r4, #TTB_FLAGS_UP) |
| 216 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 | 216 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) 217 ALT_UP(orr r8, r8, #TTB_FLAGS_UP) 218 mcr p15, 0, r8, c2, c0, 1 @ load TTB1 |
| 217#endif /* CONFIG_MMU */ 218 adr r5, v6_crval 219 ldmia r5, {r5, r6} 220#ifdef CONFIG_CPU_ENDIAN_BE8 221 orr r6, r6, #1 << 25 @ big-endian page tables 222#endif 223 mrc p15, 0, r0, c1, c0, 0 @ read control register 224 bic r0, r0, r5 @ clear bits them --- 78 unchanged lines hidden --- | 219#endif /* CONFIG_MMU */ 220 adr r5, v6_crval 221 ldmia r5, {r5, r6} 222#ifdef CONFIG_CPU_ENDIAN_BE8 223 orr r6, r6, #1 << 25 @ big-endian page tables 224#endif 225 mrc p15, 0, r0, c1, c0, 0 @ read control register 226 bic r0, r0, r5 @ clear bits them --- 78 unchanged lines hidden --- |