| cache-tauros2.c (f01387d2693813eb5271a3448e6a082322c7d75d) | cache-tauros2.c (4ed89f2228061422ce5f62545fd0b6f6648bd2cc) |
|---|---|
| 1/* 2 * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support 3 * 4 * Copyright (C) 2008 Marvell Semiconductor 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. --- 171 unchanged lines hidden (view full) --- 180 u32 u; 181 182 u = read_extra_features(); 183 184 if (features & CACHE_TAUROS2_PREFETCH_ON) 185 u &= ~0x01000000; 186 else 187 u |= 0x01000000; | 1/* 2 * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support 3 * 4 * Copyright (C) 2008 Marvell Semiconductor 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. --- 171 unchanged lines hidden (view full) --- 180 u32 u; 181 182 u = read_extra_features(); 183 184 if (features & CACHE_TAUROS2_PREFETCH_ON) 185 u &= ~0x01000000; 186 else 187 u |= 0x01000000; |
| 188 printk(KERN_INFO "Tauros2: %s L2 prefetch.\n", | 188 pr_info("Tauros2: %s L2 prefetch.\n", |
| 189 (features & CACHE_TAUROS2_PREFETCH_ON) 190 ? "Enabling" : "Disabling"); 191 192 if (features & CACHE_TAUROS2_LINEFILL_BURST8) 193 u |= 0x00100000; 194 else 195 u &= ~0x00100000; | 189 (features & CACHE_TAUROS2_PREFETCH_ON) 190 ? "Enabling" : "Disabling"); 191 192 if (features & CACHE_TAUROS2_LINEFILL_BURST8) 193 u |= 0x00100000; 194 else 195 u &= ~0x00100000; |
| 196 printk(KERN_INFO "Tauros2: %s line fill burt8.\n", | 196 pr_info("Tauros2: %s line fill burt8.\n", |
| 197 (features & CACHE_TAUROS2_LINEFILL_BURST8) 198 ? "Enabling" : "Disabling"); 199 200 write_extra_features(u); 201} 202 203static void __init tauros2_internal_init(unsigned int features) 204{ --- 6 unchanged lines hidden (view full) --- 211 u32 feat; 212 213 /* 214 * v5 CPUs with Tauros2 have the L2 cache enable bit 215 * located in the CPU Extra Features register. 216 */ 217 feat = read_extra_features(); 218 if (!(feat & 0x00400000)) { | 197 (features & CACHE_TAUROS2_LINEFILL_BURST8) 198 ? "Enabling" : "Disabling"); 199 200 write_extra_features(u); 201} 202 203static void __init tauros2_internal_init(unsigned int features) 204{ --- 6 unchanged lines hidden (view full) --- 211 u32 feat; 212 213 /* 214 * v5 CPUs with Tauros2 have the L2 cache enable bit 215 * located in the CPU Extra Features register. 216 */ 217 feat = read_extra_features(); 218 if (!(feat & 0x00400000)) { |
| 219 printk(KERN_INFO "Tauros2: Enabling L2 cache.\n"); | 219 pr_info("Tauros2: Enabling L2 cache.\n"); |
| 220 write_extra_features(feat | 0x00400000); 221 } 222 223 mode = "ARMv5"; 224 outer_cache.inv_range = tauros2_inv_range; 225 outer_cache.clean_range = tauros2_clean_range; 226 outer_cache.flush_range = tauros2_flush_range; 227 outer_cache.disable = tauros2_disable; --- 20 unchanged lines hidden (view full) --- 248 /* 249 * When Tauros2 is used in an ARMv7 system, the L2 250 * enable bit is located in the Auxiliary System Control 251 * Register (which is the only register allowed by the 252 * ARMv7 spec to contain fine-grained cache control bits). 253 */ 254 actlr = read_actlr(); 255 if (!(actlr & 0x00000002)) { | 220 write_extra_features(feat | 0x00400000); 221 } 222 223 mode = "ARMv5"; 224 outer_cache.inv_range = tauros2_inv_range; 225 outer_cache.clean_range = tauros2_clean_range; 226 outer_cache.flush_range = tauros2_flush_range; 227 outer_cache.disable = tauros2_disable; --- 20 unchanged lines hidden (view full) --- 248 /* 249 * When Tauros2 is used in an ARMv7 system, the L2 250 * enable bit is located in the Auxiliary System Control 251 * Register (which is the only register allowed by the 252 * ARMv7 spec to contain fine-grained cache control bits). 253 */ 254 actlr = read_actlr(); 255 if (!(actlr & 0x00000002)) { |
| 256 printk(KERN_INFO "Tauros2: Enabling L2 cache.\n"); | 256 pr_info("Tauros2: Enabling L2 cache.\n"); |
| 257 write_actlr(actlr | 0x00000002); 258 } 259 260 mode = "ARMv7"; 261 } 262#endif 263 264 if (mode == NULL) { | 257 write_actlr(actlr | 0x00000002); 258 } 259 260 mode = "ARMv7"; 261 } 262#endif 263 264 if (mode == NULL) { |
| 265 printk(KERN_CRIT "Tauros2: Unable to detect CPU mode.\n"); | 265 pr_crit("Tauros2: Unable to detect CPU mode.\n"); |
| 266 return; 267 } 268 | 266 return; 267 } 268 |
| 269 printk(KERN_INFO "Tauros2: L2 cache support initialised " | 269 pr_info("Tauros2: L2 cache support initialised " |
| 270 "in %s mode.\n", mode); 271} 272 273#ifdef CONFIG_OF 274static const struct of_device_id tauros2_ids[] __initconst = { 275 { .compatible = "marvell,tauros2-cache"}, 276 {} 277}; --- 25 unchanged lines hidden --- | 270 "in %s mode.\n", mode); 271} 272 273#ifdef CONFIG_OF 274static const struct of_device_id tauros2_ids[] __initconst = { 275 { .compatible = "marvell,tauros2-cache"}, 276 {} 277}; --- 25 unchanged lines hidden --- |