platsmp.c (902ef5d77aeaff43bce8d3ce55c442a12eb71819) platsmp.c (b1cffebf1029c87e1f1984d48463ee21093a6bc7)
1/*
2 * Copyright (C) 2002 ARM Ltd.
3 * Copyright (C) 2008 STMicroelctronics.
4 * Copyright (C) 2009 ST-Ericsson.
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6 *
7 * This file is based on arm realview platform
8 *

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86
87 /*
88 * The secondary processor is waiting to be released from
89 * the holding pen - release it, then wait for it to flag
90 * that it has been released by resetting pen_release.
91 */
92 write_pen_release(cpu_logical_map(cpu));
93
1/*
2 * Copyright (C) 2002 ARM Ltd.
3 * Copyright (C) 2008 STMicroelctronics.
4 * Copyright (C) 2009 ST-Ericsson.
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6 *
7 * This file is based on arm realview platform
8 *

--- 77 unchanged lines hidden (view full) ---

86
87 /*
88 * The secondary processor is waiting to be released from
89 * the holding pen - release it, then wait for it to flag
90 * that it has been released by resetting pen_release.
91 */
92 write_pen_release(cpu_logical_map(cpu));
93
94 gic_raise_softirq(cpumask_of(cpu), 0);
94 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
95
96 timeout = jiffies + (1 * HZ);
97 while (time_before(jiffies, timeout)) {
98 if (pen_release == -1)
99 break;
100 }
101
102 /*

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150 if (ncores > nr_cpu_ids) {
151 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
152 ncores, nr_cpu_ids);
153 ncores = nr_cpu_ids;
154 }
155
156 for (i = 0; i < ncores; i++)
157 set_cpu_possible(i, true);
95
96 timeout = jiffies + (1 * HZ);
97 while (time_before(jiffies, timeout)) {
98 if (pen_release == -1)
99 break;
100 }
101
102 /*

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150 if (ncores > nr_cpu_ids) {
151 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
152 ncores, nr_cpu_ids);
153 ncores = nr_cpu_ids;
154 }
155
156 for (i = 0; i < ncores; i++)
157 set_cpu_possible(i, true);
158
159 set_smp_cross_call(gic_raise_softirq);
160}
161
162static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
163{
164
165 scu_enable(scu_base_addr());
166 wakeup_secondary();
167}
168
169struct smp_operations ux500_smp_ops __initdata = {
170 .smp_init_cpus = ux500_smp_init_cpus,
171 .smp_prepare_cpus = ux500_smp_prepare_cpus,
172 .smp_secondary_init = ux500_secondary_init,
173 .smp_boot_secondary = ux500_boot_secondary,
174#ifdef CONFIG_HOTPLUG_CPU
175 .cpu_die = ux500_cpu_die,
176#endif
177};
158}
159
160static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
161{
162
163 scu_enable(scu_base_addr());
164 wakeup_secondary();
165}
166
167struct smp_operations ux500_smp_ops __initdata = {
168 .smp_init_cpus = ux500_smp_init_cpus,
169 .smp_prepare_cpus = ux500_smp_prepare_cpus,
170 .smp_secondary_init = ux500_secondary_init,
171 .smp_boot_secondary = ux500_boot_secondary,
172#ifdef CONFIG_HOTPLUG_CPU
173 .cpu_die = ux500_cpu_die,
174#endif
175};