irq.c (020abf03cd659388f94cb328e1e1df0656e0d7ff) irq.c (938fa349fbc16880feae4b65e56691ca12ede9ab)
1/*
1/*
2 * Copyright (C) 2010 Google, Inc.
2 * Copyright (C) 2011 Google, Inc.
3 *
4 * Author:
3 *
4 * Author:
5 * Colin Cross <ccross@google.com>
5 * Colin Cross <ccross@android.com>
6 *
7 * Copyright (C) 2010, NVIDIA Corporation
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,

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41#define PMC_DPD_SAMPLE 0x20
42
43static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
44
45static u32 tegra_lp0_wake_enb;
46static u32 tegra_lp0_wake_level;
47static u32 tegra_lp0_wake_level_any;
48
6 *
7 * Copyright (C) 2010, NVIDIA Corporation
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,

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41#define PMC_DPD_SAMPLE 0x20
42
43static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
44
45static u32 tegra_lp0_wake_enb;
46static u32 tegra_lp0_wake_level;
47static u32 tegra_lp0_wake_level_any;
48
49static void (*tegra_gic_mask_irq)(struct irq_data *d);
50static void (*tegra_gic_unmask_irq)(struct irq_data *d);
51static void (*tegra_gic_ack_irq)(struct irq_data *d);
52
53/* ensures that sufficient time is passed for a register write to
54 * serialize into the 32KHz domain */
55static void pmc_32kwritel(u32 val, unsigned long offs)
56{
57 writel(val, pmc + offs);
58 udelay(130);
59}
60

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98 * in which pad will be driven during lp0 mode*/
99 writel(0x1, pmc + PMC_DPD_SAMPLE);
100
101 writel(wake_enb, pmc + PMC_WAKE_MASK);
102}
103
104static void tegra_mask(struct irq_data *d)
105{
49/* ensures that sufficient time is passed for a register write to
50 * serialize into the 32KHz domain */
51static void pmc_32kwritel(u32 val, unsigned long offs)
52{
53 writel(val, pmc + offs);
54 udelay(130);
55}
56

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94 * in which pad will be driven during lp0 mode*/
95 writel(0x1, pmc + PMC_DPD_SAMPLE);
96
97 writel(wake_enb, pmc + PMC_WAKE_MASK);
98}
99
100static void tegra_mask(struct irq_data *d)
101{
106 tegra_gic_mask_irq(d);
107 tegra_legacy_mask_irq(d->irq);
102 if (d->irq >= 32)
103 tegra_legacy_mask_irq(d->irq);
108}
109
110static void tegra_unmask(struct irq_data *d)
111{
104}
105
106static void tegra_unmask(struct irq_data *d)
107{
112 tegra_gic_unmask_irq(d);
113 tegra_legacy_unmask_irq(d->irq);
108 if (d->irq >= 32)
109 tegra_legacy_unmask_irq(d->irq);
114}
115
116static void tegra_ack(struct irq_data *d)
117{
110}
111
112static void tegra_ack(struct irq_data *d)
113{
118 tegra_legacy_force_irq_clr(d->irq);
119 tegra_gic_ack_irq(d);
114 if (d->irq >= 32)
115 tegra_legacy_force_irq_clr(d->irq);
120}
121
122static int tegra_retrigger(struct irq_data *d)
123{
116}
117
118static int tegra_retrigger(struct irq_data *d)
119{
120 if (d->irq < 32)
121 return 0;
122
124 tegra_legacy_force_irq_set(d->irq);
125 return 1;
126}
127
123 tegra_legacy_force_irq_set(d->irq);
124 return 1;
125}
126
128static struct irq_chip tegra_irq = {
129 .name = "PPI",
130 .irq_ack = tegra_ack,
131 .irq_mask = tegra_mask,
132 .irq_unmask = tegra_unmask,
133 .irq_retrigger = tegra_retrigger,
134};
135
136void __init tegra_init_irq(void)
137{
127void __init tegra_init_irq(void)
128{
138 struct irq_chip *gic;
139 unsigned int i;
140 int irq;
141
142 tegra_init_legacy_irq();
143
129 tegra_init_legacy_irq();
130
131 gic_arch_extn.irq_ack = tegra_ack;
132 gic_arch_extn.irq_mask = tegra_mask;
133 gic_arch_extn.irq_unmask = tegra_unmask;
134 gic_arch_extn.irq_retrigger = tegra_retrigger;
135
144 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
145 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
136 gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
137 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
146
147 gic = irq_get_chip(29);
148 tegra_gic_unmask_irq = gic->irq_unmask;
149 tegra_gic_mask_irq = gic->irq_mask;
150 tegra_gic_ack_irq = gic->irq_ack;
151#ifdef CONFIG_SMP
152 tegra_irq.irq_set_affinity = gic->irq_set_affinity;
153#endif
154
155 for (i = 0; i < INT_MAIN_NR; i++) {
156 irq = INT_PRI_BASE + i;
157 irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
158 set_irq_flags(irq, IRQF_VALID);
159 }
160}
138}