platsmp.c (9938b04472d5c59f8bd8152a548533a8599596a2) platsmp.c (64fc2a947a9873700929ec0ef02b4654a04e0476)
1/*
2 * SMP support for Allwinner SoCs
3 *
4 * Copyright (C) 2013 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code

--- 66 unchanged lines hidden (view full) ---

75 int i;
76
77 if (!(prcm_membase && cpucfg_membase))
78 return -EFAULT;
79
80 spin_lock(&cpu_lock);
81
82 /* Set CPU boot address */
1/*
2 * SMP support for Allwinner SoCs
3 *
4 * Copyright (C) 2013 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * Based on code

--- 66 unchanged lines hidden (view full) ---

75 int i;
76
77 if (!(prcm_membase && cpucfg_membase))
78 return -EFAULT;
79
80 spin_lock(&cpu_lock);
81
82 /* Set CPU boot address */
83 writel(virt_to_phys(secondary_startup),
83 writel(__pa_symbol(secondary_startup),
84 cpucfg_membase + CPUCFG_PRIVATE0_REG);
85
86 /* Assert the CPU core in reset */
87 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
88
89 /* Assert the L1 cache in reset */
90 reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
91 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);

--- 65 unchanged lines hidden (view full) ---

157 u32 reg;
158
159 if (!(prcm_membase && cpucfg_membase))
160 return -EFAULT;
161
162 spin_lock(&cpu_lock);
163
164 /* Set CPU boot address */
84 cpucfg_membase + CPUCFG_PRIVATE0_REG);
85
86 /* Assert the CPU core in reset */
87 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
88
89 /* Assert the L1 cache in reset */
90 reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
91 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);

--- 65 unchanged lines hidden (view full) ---

157 u32 reg;
158
159 if (!(prcm_membase && cpucfg_membase))
160 return -EFAULT;
161
162 spin_lock(&cpu_lock);
163
164 /* Set CPU boot address */
165 writel(virt_to_phys(secondary_startup),
165 writel(__pa_symbol(secondary_startup),
166 cpucfg_membase + CPUCFG_PRIVATE0_REG);
167
168 /* Assert the CPU core in reset */
169 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
170
171 /* Assert the L1 cache in reset */
172 reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
173 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);

--- 19 unchanged lines hidden --- 		166 cpucfg_membase + CPUCFG_PRIVATE0_REG);
167
168 /* Assert the CPU core in reset */
169 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
170
171 /* Assert the L1 cache in reset */
172 reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
173 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);

--- 19 unchanged lines hidden ---