pxa3xx.c (4ba24fef3eb3b142197135223b90ced2f319cd53) pxa3xx.c (a1c0a6adbc705a9a760416796ce9cb3349fd476f)
1/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
8 * 2007-09-02: eric miao <eric.miao@marvell.com>

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32#include <linux/platform_data/usb-ohci-pxa27x.h>
33#include <mach/pm.h>
34#include <mach/dma.h>
35#include <mach/smemc.h>
36#include <mach/irqs.h>
37
38#include "generic.h"
39#include "devices.h"
1/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
8 * 2007-09-02: eric miao <eric.miao@marvell.com>

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32#include <linux/platform_data/usb-ohci-pxa27x.h>
33#include <mach/pm.h>
34#include <mach/dma.h>
35#include <mach/smemc.h>
36#include <mach/irqs.h>
37
38#include "generic.h"
39#include "devices.h"
40#include "clock.h"
41
42#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
43#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
44
45extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
40
41#define PECR_IE(n) ((1 << ((n) * 2)) << 28)
42#define PECR_IS(n) ((1 << ((n) * 2)) << 29)
43
44extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
46
47static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
48static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
49static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
50static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
51static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
52static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
53static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
54static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
55static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
56static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
57static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
58static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
59static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
60static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
61static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
62static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
63static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);
64
65static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
66static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
67static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
68static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
69static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
70
71static struct clk_lookup pxa3xx_clkregs[] = {
72 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
73 /* Power I2C clock is always on */
74 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
75 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
76 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
77 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
78 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
79 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
80 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
81 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
82 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
83 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
84 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
85 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
86 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
87 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa3xx-ssp.0", NULL),
88 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa3xx-ssp.1", NULL),
89 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa3xx-ssp.2", NULL),
90 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa3xx-ssp.3", NULL),
91 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
92 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
93 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
94 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
95 INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
96 INIT_CLKREG(&clk_pxa3xx_gpio, "pxa3xx-gpio", NULL),
97 INIT_CLKREG(&clk_pxa3xx_gpio, "pxa93x-gpio", NULL),
98 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
99};
100
101#ifdef CONFIG_PM
102
103#define ISRAM_START 0x5c000000
104#define ISRAM_SIZE SZ_256K
105
106static void __iomem *sram;
107static unsigned long wakeup_src;
108

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471 /*
472 * clear RDH bit every time after reset
473 *
474 * Note: the last 3 bits DxS are write-1-to-clear so carefully
475 * preserve them here in case they will be referenced later
476 */
477 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
478
45#ifdef CONFIG_PM
46
47#define ISRAM_START 0x5c000000
48#define ISRAM_SIZE SZ_256K
49
50static void __iomem *sram;
51static unsigned long wakeup_src;
52

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415 /*
416 * clear RDH bit every time after reset
417 *
418 * Note: the last 3 bits DxS are write-1-to-clear so carefully
419 * preserve them here in case they will be referenced later
420 */
421 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
422
479 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
480
481 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
482 return ret;
483
484 pxa3xx_init_pm();
485
486 register_syscore_ops(&pxa_irq_syscore_ops);
487 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
423 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
424 return ret;
425
426 pxa3xx_init_pm();
427
428 register_syscore_ops(&pxa_irq_syscore_ops);
429 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
488 register_syscore_ops(&pxa3xx_clock_syscore_ops);
489
490 if (of_have_populated_dt())
491 return 0;
492
493 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
494 if (ret)
495 return ret;
496 if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
497 platform_device_add_data(&pxa3xx_device_gpio,
498 &pxa3xx_gpio_pdata,
499 sizeof(pxa3xx_gpio_pdata));
500 ret = platform_device_register(&pxa3xx_device_gpio);
501 }
502 }
503
504 return ret;
505}
506
507postcore_initcall(pxa3xx_init);
430
431 if (of_have_populated_dt())
432 return 0;
433
434 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
435 if (ret)
436 return ret;
437 if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
438 platform_device_add_data(&pxa3xx_device_gpio,
439 &pxa3xx_gpio_pdata,
440 sizeof(pxa3xx_gpio_pdata));
441 ret = platform_device_register(&pxa3xx_device_gpio);
442 }
443 }
444
445 return ret;
446}
447
448postcore_initcall(pxa3xx_init);