generic.c (b10f1c836c4e8c2372d14953a17aa5b9744eb55c) generic.c (a38b1f60b5245a3f610baac2019c0ecd8abd8752)
1/*
2 * linux/arch/arm/mach-pxa/generic.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code common to all PXA machines.

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20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23
24#include <mach/hardware.h>
25#include <asm/mach/map.h>
26#include <asm/mach-types.h>
27
1/*
2 * linux/arch/arm/mach-pxa/generic.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code common to all PXA machines.

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20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23
24#include <mach/hardware.h>
25#include <asm/mach/map.h>
26#include <asm/mach-types.h>
27
28#include <mach/irqs.h>
28#include <mach/reset.h>
29#include <mach/smemc.h>
30#include <mach/pxa3xx-regs.h>
31
32#include "generic.h"
29#include <mach/reset.h>
30#include <mach/smemc.h>
31#include <mach/pxa3xx-regs.h>
32
33#include "generic.h"
34#include <clocksource/pxa.h>
33
34void clear_reset_status(unsigned int mask)
35{
36 if (cpu_is_pxa2xx())
37 pxa2xx_clear_reset_status(mask);
38 else {
39 /* RESET_STATUS_* has a 1:1 mapping with ARSR */
40 ARSR = mask;

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52 else
53 clock_tick_rate = 3250000;
54
55 return clock_tick_rate;
56}
57EXPORT_SYMBOL(get_clock_tick_rate);
58
59/*
35
36void clear_reset_status(unsigned int mask)
37{
38 if (cpu_is_pxa2xx())
39 pxa2xx_clear_reset_status(mask);
40 else {
41 /* RESET_STATUS_* has a 1:1 mapping with ARSR */
42 ARSR = mask;

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54 else
55 clock_tick_rate = 3250000;
56
57 return clock_tick_rate;
58}
59EXPORT_SYMBOL(get_clock_tick_rate);
60
61/*
62 * For non device-tree builds, keep legacy timer init
63 */
64void pxa_timer_init(void)
65{
66 pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000),
67 get_clock_tick_rate());
68}
69
70/*
60 * Get the clock frequency as reflected by CCCR and the turbo flag.
61 * We assume these values have been applied via a fcs.
62 * If info is not 0 we also display the current settings.
63 */
64unsigned int get_clk_frequency_khz(int info)
65{
66 if (cpu_is_pxa25x())
67 return pxa25x_get_clk_frequency_khz(info);

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74/*
75 * Intel PXA2xx internal register mapping.
76 *
77 * Note: virtual 0xfffe0000-0xffffffff is reserved for the vector table
78 * and cache flush area.
79 */
80static struct map_desc common_io_desc[] __initdata = {
81 { /* Devs */
71 * Get the clock frequency as reflected by CCCR and the turbo flag.
72 * We assume these values have been applied via a fcs.
73 * If info is not 0 we also display the current settings.
74 */
75unsigned int get_clk_frequency_khz(int info)
76{
77 if (cpu_is_pxa25x())
78 return pxa25x_get_clk_frequency_khz(info);

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85/*
86 * Intel PXA2xx internal register mapping.
87 *
88 * Note: virtual 0xfffe0000-0xffffffff is reserved for the vector table
89 * and cache flush area.
90 */
91static struct map_desc common_io_desc[] __initdata = {
92 { /* Devs */
82 .virtual = (unsigned long)PERIPH_VIRT,
83 .pfn = __phys_to_pfn(PERIPH_PHYS),
84 .length = PERIPH_SIZE,
93 .virtual = 0xf2000000,
94 .pfn = __phys_to_pfn(0x40000000),
95 .length = 0x02000000,
85 .type = MT_DEVICE
96 .type = MT_DEVICE
97 }, { /* UNCACHED_PHYS_0 */
98 .virtual = 0xff000000,
99 .pfn = __phys_to_pfn(0x00000000),
100 .length = 0x00100000,
101 .type = MT_DEVICE
86 }
87};
88
89void __init pxa_map_io(void)
90{
102 }
103};
104
105void __init pxa_map_io(void)
106{
91 debug_ll_io_init();
92 iotable_init(ARRAY_AND_SIZE(common_io_desc));
93}
107 iotable_init(ARRAY_AND_SIZE(common_io_desc));
108}