| sleep43xx.S (74655749a58405e259eaaba66bfc391fdbe1e34e) | sleep43xx.S (8c5a916f4c8815196cc8a86b9582ca89422aac25) |
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| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Low level suspend code for AM43XX SoCs 4 * 5 * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 6 * Dave Gerlach, Vaibhav Bedia 7 */ 8 --- 34 unchanged lines hidden (view full) --- 43#define AM43XX_CM_MPU_CLKSTCTRL AM43XX_CM_REGADDR(AM43XX_CM_MPU_INST, \ 44 AM43XX_CM_MPU_MPU_CDOFFS) 45#define AM43XX_CM_MPU_MPU_CLKCTRL AM43XX_CM_REGADDR(AM43XX_CM_MPU_INST, \ 46 AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET) 47#define AM43XX_CM_PER_EMIF_CLKCTRL AM43XX_CM_REGADDR(AM43XX_CM_PER_INST, \ 48 AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET) 49#define AM43XX_PRM_EMIF_CTRL_OFFSET 0x0030 50 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Low level suspend code for AM43XX SoCs 4 * 5 * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ 6 * Dave Gerlach, Vaibhav Bedia 7 */ 8 --- 34 unchanged lines hidden (view full) --- 43#define AM43XX_CM_MPU_CLKSTCTRL AM43XX_CM_REGADDR(AM43XX_CM_MPU_INST, \ 44 AM43XX_CM_MPU_MPU_CDOFFS) 45#define AM43XX_CM_MPU_MPU_CLKCTRL AM43XX_CM_REGADDR(AM43XX_CM_MPU_INST, \ 46 AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET) 47#define AM43XX_CM_PER_EMIF_CLKCTRL AM43XX_CM_REGADDR(AM43XX_CM_PER_INST, \ 48 AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET) 49#define AM43XX_PRM_EMIF_CTRL_OFFSET 0x0030 50 |
| 51#define RTC_SECONDS_REG 0x0 52#define RTC_PMIC_REG 0x98 53#define RTC_PMIC_POWER_EN BIT(16) 54#define RTC_PMIC_EXT_WAKEUP_STS BIT(12) 55#define RTC_PMIC_EXT_WAKEUP_POL BIT(4) 56#define RTC_PMIC_EXT_WAKEUP_EN BIT(0) 57 |
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| 51 .arm 52 .align 3 53 54ENTRY(am43xx_do_wfi) 55 stmfd sp!, {r4 - r11, lr} @ save registers on stack 56 57 /* Save wfi_flags arg to data space */ 58 mov r4, r0 --- 83 unchanged lines hidden (view full) --- 142#endif 143 144 /* Restore wfi_flags */ 145 adr r3, am43xx_pm_ro_sram_data 146 ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET] 147 ldr r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET] 148 149cache_skip_flush: | 58 .arm 59 .align 3 60 61ENTRY(am43xx_do_wfi) 62 stmfd sp!, {r4 - r11, lr} @ save registers on stack 63 64 /* Save wfi_flags arg to data space */ 65 mov r4, r0 --- 83 unchanged lines hidden (view full) --- 149#endif 150 151 /* Restore wfi_flags */ 152 adr r3, am43xx_pm_ro_sram_data 153 ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET] 154 ldr r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET] 155 156cache_skip_flush: |
| 157 /* 158 * If we are trying to enter RTC+DDR mode we must perform 159 * a read from the rtc address space to ensure translation 160 * presence in the TLB to avoid page table walk after DDR 161 * is unavailable. 162 */ 163 tst r4, #WFI_FLAG_RTC_ONLY 164 beq skip_rtc_va_refresh 165 166 adr r3, am43xx_pm_ro_sram_data 167 ldr r1, [r3, #AMX3_PM_RTC_BASE_VIRT_OFFSET] 168 ldr r0, [r1] 169 170skip_rtc_va_refresh: |
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| 150 /* Check if we want self refresh */ 151 tst r4, #WFI_FLAG_SELF_REFRESH 152 beq emif_skip_enter_sr 153 154 adr r9, am43xx_emif_sram_table 155 156 ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET] 157 blx r3 --- 19 unchanged lines hidden (view full) --- 177 178wait_emif_disable: 179 ldr r2, [r1] 180 mov r3, #AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED 181 cmp r2, r3 182 bne wait_emif_disable 183 184emif_skip_disable: | 171 /* Check if we want self refresh */ 172 tst r4, #WFI_FLAG_SELF_REFRESH 173 beq emif_skip_enter_sr 174 175 adr r9, am43xx_emif_sram_table 176 177 ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET] 178 blx r3 --- 19 unchanged lines hidden (view full) --- 198 199wait_emif_disable: 200 ldr r2, [r1] 201 mov r3, #AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED 202 cmp r2, r3 203 bne wait_emif_disable 204 205emif_skip_disable: |
| 206 tst r4, #WFI_FLAG_RTC_ONLY 207 beq skip_rtc_only 208 209 adr r3, am43xx_pm_ro_sram_data 210 ldr r1, [r3, #AMX3_PM_RTC_BASE_VIRT_OFFSET] 211 212 ldr r0, [r1, #RTC_PMIC_REG] 213 orr r0, r0, #RTC_PMIC_POWER_EN 214 orr r0, r0, #RTC_PMIC_EXT_WAKEUP_STS 215 orr r0, r0, #RTC_PMIC_EXT_WAKEUP_EN 216 orr r0, r0, #RTC_PMIC_EXT_WAKEUP_POL 217 str r0, [r1, #RTC_PMIC_REG] 218 ldr r0, [r1, #RTC_PMIC_REG] 219 /* Wait for 2 seconds to lose power */ 220 mov r3, #2 221 ldr r2, [r1, #RTC_SECONDS_REG] 222rtc_loop: 223 ldr r0, [r1, #RTC_SECONDS_REG] 224 cmp r0, r2 225 beq rtc_loop 226 mov r2, r0 227 subs r3, r3, #1 228 bne rtc_loop 229 230 b re_enable_emif 231 232skip_rtc_only: 233 |
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| 185 tst r4, #WFI_FLAG_WAKE_M3 186 beq wkup_m3_skip 187 188 /* 189 * For the MPU WFI to be registered as an interrupt 190 * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set 191 * to DISABLED 192 */ --- 49 unchanged lines hidden (view full) --- 242 mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO 243 str r2, [r1] 244 245 /* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */ 246 ldr r1, am43xx_virt_mpu_clkctrl 247 mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 248 str r2, [r1] 249 | 234 tst r4, #WFI_FLAG_WAKE_M3 235 beq wkup_m3_skip 236 237 /* 238 * For the MPU WFI to be registered as an interrupt 239 * to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set 240 * to DISABLED 241 */ --- 49 unchanged lines hidden (view full) --- 291 mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO 292 str r2, [r1] 293 294 /* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */ 295 ldr r1, am43xx_virt_mpu_clkctrl 296 mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 297 str r2, [r1] 298 |
| 299re_enable_emif: |
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| 250 /* Re-enable EMIF */ 251 ldr r1, am43xx_virt_emif_clkctrl 252 mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 253 str r2, [r1] 254wait_emif_enable: 255 ldr r3, [r1] 256 cmp r2, r3 257 bne wait_emif_enable --- 118 unchanged lines hidden (view full) --- 376 mov r0, #0 377 ldr pc, resume_addr 378ENDPROC(am43xx_resume_from_deep_sleep) 379 380/* 381 * Local variables 382 */ 383 .align | 300 /* Re-enable EMIF */ 301 ldr r1, am43xx_virt_emif_clkctrl 302 mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 303 str r2, [r1] 304wait_emif_enable: 305 ldr r3, [r1] 306 cmp r2, r3 307 bne wait_emif_enable --- 118 unchanged lines hidden (view full) --- 426 mov r0, #0 427 ldr pc, resume_addr 428ENDPROC(am43xx_resume_from_deep_sleep) 429 430/* 431 * Local variables 432 */ 433 .align |
| 384resume_addr: 385 .word cpu_resume - PAGE_OFFSET + 0x80000000 | |
| 386kernel_flush: 387 .word v7_flush_dcache_all 388ddr_start: 389 .word PAGE_OFFSET 390 391am43xx_phys_emif_poweroff: 392 .word (AM43XX_CM_BASE + AM43XX_PRM_DEVICE_INST + \ 393 AM43XX_PRM_EMIF_CTRL_OFFSET) --- 30 unchanged lines hidden (view full) --- 424 425ENTRY(am43xx_pm_sram) 426 .word am43xx_do_wfi 427 .word am43xx_do_wfi_sz 428 .word am43xx_resume_offset 429 .word am43xx_emif_sram_table 430 .word am43xx_pm_ro_sram_data 431 | 434kernel_flush: 435 .word v7_flush_dcache_all 436ddr_start: 437 .word PAGE_OFFSET 438 439am43xx_phys_emif_poweroff: 440 .word (AM43XX_CM_BASE + AM43XX_PRM_DEVICE_INST + \ 441 AM43XX_PRM_EMIF_CTRL_OFFSET) --- 30 unchanged lines hidden (view full) --- 472 473ENTRY(am43xx_pm_sram) 474 .word am43xx_do_wfi 475 .word am43xx_do_wfi_sz 476 .word am43xx_resume_offset 477 .word am43xx_emif_sram_table 478 .word am43xx_pm_ro_sram_data 479 |
| 480resume_addr: 481 .word cpu_resume - PAGE_OFFSET + 0x80000000 |
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| 432.align 3 433 434ENTRY(am43xx_pm_ro_sram_data) 435 .space AMX3_PM_RO_SRAM_DATA_SIZE 436 437ENTRY(am43xx_do_wfi_sz) 438 .word . - am43xx_do_wfi | 482.align 3 483 484ENTRY(am43xx_pm_ro_sram_data) 485 .space AMX3_PM_RO_SRAM_DATA_SIZE 486 487ENTRY(am43xx_do_wfi_sz) 488 .word . - am43xx_do_wfi |