sleep43xx.S (18b4788badeae8ed3a9bd3c240d83dffe5db8f37) sleep43xx.S (03de3727b25059d9802d1baac319ba40c035eade)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Low level suspend code for AM43XX SoCs
4 *
5 * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Dave Gerlach, Vaibhav Bedia
7 */
8

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47#define AM43XX_PRM_EMIF_CTRL_OFFSET 0x0030
48
49 .arm
50 .align 3
51
52ENTRY(am43xx_do_wfi)
53 stmfd sp!, {r4 - r11, lr} @ save registers on stack
54
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Low level suspend code for AM43XX SoCs
4 *
5 * Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Dave Gerlach, Vaibhav Bedia
7 */
8

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47#define AM43XX_PRM_EMIF_CTRL_OFFSET 0x0030
48
49 .arm
50 .align 3
51
52ENTRY(am43xx_do_wfi)
53 stmfd sp!, {r4 - r11, lr} @ save registers on stack
54
55#ifdef CONFIG_CACHE_L2X0
55 /* Retrieve l2 cache virt address BEFORE we shut off EMIF */
56 ldr r1, get_l2cache_base
57 blx r1
58 mov r8, r0
56 /* Retrieve l2 cache virt address BEFORE we shut off EMIF */
57 ldr r1, get_l2cache_base
58 blx r1
59 mov r8, r0
60#endif
59
60 /*
61 * Flush all data from the L1 and L2 data cache before disabling
62 * SCTLR.C bit.
63 */
64 ldr r1, kernel_flush
65 blx r1
66

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329ENDPROC(am43xx_resume_from_deep_sleep)
330
331/*
332 * Local variables
333 */
334 .align
335resume_addr:
336 .word cpu_resume - PAGE_OFFSET + 0x80000000
61
62 /*
63 * Flush all data from the L1 and L2 data cache before disabling
64 * SCTLR.C bit.
65 */
66 ldr r1, kernel_flush
67 blx r1
68

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331ENDPROC(am43xx_resume_from_deep_sleep)
332
333/*
334 * Local variables
335 */
336 .align
337resume_addr:
338 .word cpu_resume - PAGE_OFFSET + 0x80000000
337get_l2cache_base:
338 .word omap4_get_l2cache_base
339kernel_flush:
340 .word v7_flush_dcache_all
341ddr_start:
342 .word PAGE_OFFSET
343
344am43xx_phys_emif_poweroff:
345 .word (AM43XX_CM_BASE + AM43XX_PRM_DEVICE_INST + \
346 AM43XX_PRM_EMIF_CTRL_OFFSET)
347am43xx_virt_mpu_clkstctrl:
348 .word (AM43XX_CM_MPU_CLKSTCTRL)
349am43xx_virt_mpu_clkctrl:
350 .word (AM43XX_CM_MPU_MPU_CLKCTRL)
351am43xx_virt_emif_clkctrl:
352 .word (AM43XX_CM_PER_EMIF_CLKCTRL)
353am43xx_phys_emif_clkctrl:
354 .word (AM43XX_CM_BASE + AM43XX_CM_PER_INST + \
355 AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET)
356
339kernel_flush:
340 .word v7_flush_dcache_all
341ddr_start:
342 .word PAGE_OFFSET
343
344am43xx_phys_emif_poweroff:
345 .word (AM43XX_CM_BASE + AM43XX_PRM_DEVICE_INST + \
346 AM43XX_PRM_EMIF_CTRL_OFFSET)
347am43xx_virt_mpu_clkstctrl:
348 .word (AM43XX_CM_MPU_CLKSTCTRL)
349am43xx_virt_mpu_clkctrl:
350 .word (AM43XX_CM_MPU_MPU_CLKCTRL)
351am43xx_virt_emif_clkctrl:
352 .word (AM43XX_CM_PER_EMIF_CLKCTRL)
353am43xx_phys_emif_clkctrl:
354 .word (AM43XX_CM_BASE + AM43XX_CM_PER_INST + \
355 AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET)
356
357#ifdef CONFIG_CACHE_L2X0
357/* L2 cache related defines for AM437x */
358/* L2 cache related defines for AM437x */
359get_l2cache_base:
360 .word omap4_get_l2cache_base
358l2_cache_base:
359 .word OMAP44XX_L2CACHE_BASE
360l2_smc1:
361 .word OMAP4_MON_L2X0_PREFETCH_INDEX
362l2_smc2:
363 .word OMAP4_MON_L2X0_AUXCTRL_INDEX
364l2_smc3:
365 .word OMAP4_MON_L2X0_CTRL_INDEX
366l2_val:
367 .word 0xffff
361l2_cache_base:
362 .word OMAP44XX_L2CACHE_BASE
363l2_smc1:
364 .word OMAP4_MON_L2X0_PREFETCH_INDEX
365l2_smc2:
366 .word OMAP4_MON_L2X0_AUXCTRL_INDEX
367l2_smc3:
368 .word OMAP4_MON_L2X0_CTRL_INDEX
369l2_val:
370 .word 0xffff
371#endif
368
369.align 3
370/* DDR related defines */
371ENTRY(am43xx_emif_sram_table)
372 .space EMIF_PM_FUNCTIONS_SIZE
373
374ENTRY(am43xx_pm_sram)
375 .word am43xx_do_wfi

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373.align 3
374/* DDR related defines */
375ENTRY(am43xx_emif_sram_table)
376 .space EMIF_PM_FUNCTIONS_SIZE
377
378ENTRY(am43xx_pm_sram)
379 .word am43xx_do_wfi

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