pm34xx.c (f0611a5c220e50dec65041b10bd2fe9484f061a6) pm34xx.c (c4d7e58fb52c632d8e33cd23a4917d7a7f8302ac)
1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.

--- 91 unchanged lines hidden (view full) ---

100 omap_gpio_restore_context();
101}
102
103static void omap3_enable_io_chain(void)
104{
105 int timeout = 0;
106
107 if (omap_rev() >= OMAP3430_REV_ES3_1) {
1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.

--- 91 unchanged lines hidden (view full) ---

100 omap_gpio_restore_context();
101}
102
103static void omap3_enable_io_chain(void)
104{
105 int timeout = 0;
106
107 if (omap_rev() >= OMAP3430_REV_ES3_1) {
108 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
108 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
109 PM_WKEN);
110 /* Do a readback to assure write has been done */
109 PM_WKEN);
110 /* Do a readback to assure write has been done */
111 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
111 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
112
112
113 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
113 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
114 OMAP3430_ST_IO_CHAIN_MASK)) {
115 timeout++;
116 if (timeout > 1000) {
117 printk(KERN_ERR "Wake up daisy chain "
118 "activation failed.\n");
119 return;
120 }
114 OMAP3430_ST_IO_CHAIN_MASK)) {
115 timeout++;
116 if (timeout > 1000) {
117 printk(KERN_ERR "Wake up daisy chain "
118 "activation failed.\n");
119 return;
120 }
121 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
121 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
122 WKUP_MOD, PM_WKEN);
123 }
124 }
125}
126
127static void omap3_disable_io_chain(void)
128{
129 if (omap_rev() >= OMAP3430_REV_ES3_1)
122 WKUP_MOD, PM_WKEN);
123 }
124 }
125}
126
127static void omap3_disable_io_chain(void)
128{
129 if (omap_rev() >= OMAP3430_REV_ES3_1)
130 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
130 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
131 PM_WKEN);
132}
133
134static void omap3_core_save_context(void)
135{
136 u32 control_padconf_off;
137
138 /* Save the padconf registers */

--- 77 unchanged lines hidden (view full) ---

216 u32 wkst, fclk, iclk, clken;
217 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
218 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
219 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
220 u16 grpsel_off = (regs == 3) ?
221 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
222 int c = 0;
223
131 PM_WKEN);
132}
133
134static void omap3_core_save_context(void)
135{
136 u32 control_padconf_off;
137
138 /* Save the padconf registers */

--- 77 unchanged lines hidden (view full) ---

216 u32 wkst, fclk, iclk, clken;
217 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
218 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
219 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
220 u16 grpsel_off = (regs == 3) ?
221 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
222 int c = 0;
223
224 wkst = prm_read_mod_reg(module, wkst_off);
225 wkst &= prm_read_mod_reg(module, grpsel_off);
224 wkst = omap2_prm_read_mod_reg(module, wkst_off);
225 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
226 if (wkst) {
226 if (wkst) {
227 iclk = cm_read_mod_reg(module, iclk_off);
228 fclk = cm_read_mod_reg(module, fclk_off);
227 iclk = omap2_cm_read_mod_reg(module, iclk_off);
228 fclk = omap2_cm_read_mod_reg(module, fclk_off);
229 while (wkst) {
230 clken = wkst;
229 while (wkst) {
230 clken = wkst;
231 cm_set_mod_reg_bits(clken, module, iclk_off);
231 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
232 /*
233 * For USBHOST, we don't know whether HOST1 or
234 * HOST2 woke us up, so enable both f-clocks
235 */
236 if (module == OMAP3430ES2_USBHOST_MOD)
237 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
232 /*
233 * For USBHOST, we don't know whether HOST1 or
234 * HOST2 woke us up, so enable both f-clocks
235 */
236 if (module == OMAP3430ES2_USBHOST_MOD)
237 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
238 cm_set_mod_reg_bits(clken, module, fclk_off);
239 prm_write_mod_reg(wkst, module, wkst_off);
240 wkst = prm_read_mod_reg(module, wkst_off);
238 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
239 omap2_prm_write_mod_reg(wkst, module, wkst_off);
240 wkst = omap2_prm_read_mod_reg(module, wkst_off);
241 c++;
242 }
241 c++;
242 }
243 cm_write_mod_reg(iclk, module, iclk_off);
244 cm_write_mod_reg(fclk, module, fclk_off);
243 omap2_cm_write_mod_reg(iclk, module, iclk_off);
244 omap2_cm_write_mod_reg(fclk, module, fclk_off);
245 }
246
247 return c;
248}
249
250static int _prcm_int_handle_wakeup(void)
251{
252 int c;

--- 26 unchanged lines hidden (view full) ---

279 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
280 * this would be handled.
281 */
282static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
283{
284 u32 irqenable_mpu, irqstatus_mpu;
285 int c = 0;
286
245 }
246
247 return c;
248}
249
250static int _prcm_int_handle_wakeup(void)
251{
252 int c;

--- 26 unchanged lines hidden (view full) ---

279 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
280 * this would be handled.
281 */
282static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
283{
284 u32 irqenable_mpu, irqstatus_mpu;
285 int c = 0;
286
287 irqenable_mpu = prm_read_mod_reg(OCP_MOD,
287 irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
288 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
288 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
289 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
289 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
290 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
291 irqstatus_mpu &= irqenable_mpu;
292
293 do {
294 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
295 OMAP3430_IO_ST_MASK)) {
296 c = _prcm_int_handle_wakeup();
297

--- 4 unchanged lines hidden (view full) ---

302 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
303 "but no wakeup sources are marked\n");
304 } else {
305 /* XXX we need to expand our PRCM interrupt handler */
306 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
307 "no code to handle it (%08x)\n", irqstatus_mpu);
308 }
309
290 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
291 irqstatus_mpu &= irqenable_mpu;
292
293 do {
294 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
295 OMAP3430_IO_ST_MASK)) {
296 c = _prcm_int_handle_wakeup();
297

--- 4 unchanged lines hidden (view full) ---

302 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
303 "but no wakeup sources are marked\n");
304 } else {
305 /* XXX we need to expand our PRCM interrupt handler */
306 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
307 "no code to handle it (%08x)\n", irqstatus_mpu);
308 }
309
310 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
310 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
311 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
312
311 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
312
313 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
313 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
314 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
315 irqstatus_mpu &= irqenable_mpu;
316
317 } while (irqstatus_mpu);
318
319 return IRQ_HANDLED;
320}
321

--- 71 unchanged lines hidden (view full) ---

393 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
394
395 /* Enable IO-PAD and IO-CHAIN wakeups */
396 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
397 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
398 if (omap3_has_io_wakeup() &&
399 (per_next_state < PWRDM_POWER_ON ||
400 core_next_state < PWRDM_POWER_ON)) {
314 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
315 irqstatus_mpu &= irqenable_mpu;
316
317 } while (irqstatus_mpu);
318
319 return IRQ_HANDLED;
320}
321

--- 71 unchanged lines hidden (view full) ---

393 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
394
395 /* Enable IO-PAD and IO-CHAIN wakeups */
396 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
397 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
398 if (omap3_has_io_wakeup() &&
399 (per_next_state < PWRDM_POWER_ON ||
400 core_next_state < PWRDM_POWER_ON)) {
401 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
401 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
402 omap3_enable_io_chain();
403 }
404
405 /* Block console output in case it is on one of the OMAP UARTs */
406 if (!is_suspending())
407 if (per_next_state < PWRDM_POWER_ON ||
408 core_next_state < PWRDM_POWER_ON)
409 if (try_acquire_console_sem())

--- 56 unchanged lines hidden (view full) ---

466 omap3_core_restore_context();
467 omap3_cm_restore_context();
468 omap3_sram_restore_context();
469 omap2_sms_restore_context();
470 }
471 omap_uart_resume_idle(0);
472 omap_uart_resume_idle(1);
473 if (core_next_state == PWRDM_POWER_OFF)
402 omap3_enable_io_chain();
403 }
404
405 /* Block console output in case it is on one of the OMAP UARTs */
406 if (!is_suspending())
407 if (per_next_state < PWRDM_POWER_ON ||
408 core_next_state < PWRDM_POWER_ON)
409 if (try_acquire_console_sem())

--- 56 unchanged lines hidden (view full) ---

466 omap3_core_restore_context();
467 omap3_cm_restore_context();
468 omap3_sram_restore_context();
469 omap2_sms_restore_context();
470 }
471 omap_uart_resume_idle(0);
472 omap_uart_resume_idle(1);
473 if (core_next_state == PWRDM_POWER_OFF)
474 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
474 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
475 OMAP3430_GR_MOD,
476 OMAP3_PRM_VOLTCTRL_OFFSET);
477 }
478 omap3_intc_resume_idle();
479
480 /* PER */
481 if (per_next_state < PWRDM_POWER_ON) {
482 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);

--- 7 unchanged lines hidden (view full) ---

490 if (!is_suspending())
491 release_console_sem();
492
493console_still_active:
494 /* Disable IO-PAD and IO-CHAIN wakeup */
495 if (omap3_has_io_wakeup() &&
496 (per_next_state < PWRDM_POWER_ON ||
497 core_next_state < PWRDM_POWER_ON)) {
475 OMAP3430_GR_MOD,
476 OMAP3_PRM_VOLTCTRL_OFFSET);
477 }
478 omap3_intc_resume_idle();
479
480 /* PER */
481 if (per_next_state < PWRDM_POWER_ON) {
482 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);

--- 7 unchanged lines hidden (view full) ---

490 if (!is_suspending())
491 release_console_sem();
492
493console_still_active:
494 /* Disable IO-PAD and IO-CHAIN wakeup */
495 if (omap3_has_io_wakeup() &&
496 (per_next_state < PWRDM_POWER_ON ||
497 core_next_state < PWRDM_POWER_ON)) {
498 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
498 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
499 PM_WKEN);
499 omap3_disable_io_chain();
500 }
501
502 pwrdm_post_transition();
503
504 omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
505}
506

--- 121 unchanged lines hidden (view full) ---

628 * full-chip retention or off-mode because it is not idle. This
629 * function forces the IVA2 into idle state so it can go
630 * into retention/off and thus allow full-chip retention/off.
631 *
632 **/
633static void __init omap3_iva_idle(void)
634{
635 /* ensure IVA2 clock is disabled */
500 omap3_disable_io_chain();
501 }
502
503 pwrdm_post_transition();
504
505 omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
506}
507

--- 121 unchanged lines hidden (view full) ---

629 * full-chip retention or off-mode because it is not idle. This
630 * function forces the IVA2 into idle state so it can go
631 * into retention/off and thus allow full-chip retention/off.
632 *
633 **/
634static void __init omap3_iva_idle(void)
635{
636 /* ensure IVA2 clock is disabled */
636 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
637 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
637
638 /* if no clock activity, nothing else to do */
638
639 /* if no clock activity, nothing else to do */
639 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
640 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
640 OMAP3430_CLKACTIVITY_IVA2_MASK))
641 return;
642
643 /* Reset IVA2 */
641 OMAP3430_CLKACTIVITY_IVA2_MASK))
642 return;
643
644 /* Reset IVA2 */
644 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
645 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
645 OMAP3430_RST2_IVA2_MASK |
646 OMAP3430_RST3_IVA2_MASK,
647 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
648
649 /* Enable IVA2 clock */
646 OMAP3430_RST2_IVA2_MASK |
647 OMAP3430_RST3_IVA2_MASK,
648 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
649
650 /* Enable IVA2 clock */
650 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
651 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
651 OMAP3430_IVA2_MOD, CM_FCLKEN);
652
653 /* Set IVA2 boot mode to 'idle' */
654 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
655 OMAP343X_CONTROL_IVA2_BOOTMOD);
656
657 /* Un-reset IVA2 */
652 OMAP3430_IVA2_MOD, CM_FCLKEN);
653
654 /* Set IVA2 boot mode to 'idle' */
655 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
656 OMAP343X_CONTROL_IVA2_BOOTMOD);
657
658 /* Un-reset IVA2 */
658 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
659 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
659
660 /* Disable IVA2 clock */
660
661 /* Disable IVA2 clock */
661 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
662 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
662
663 /* Reset IVA2 */
663
664 /* Reset IVA2 */
664 prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
665 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
665 OMAP3430_RST2_IVA2_MASK |
666 OMAP3430_RST3_IVA2_MASK,
667 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
668}
669
670static void __init omap3_d2d_idle(void)
671{
672 u16 mask, padconf;

--- 7 unchanged lines hidden (view full) ---

680 padconf |= mask;
681 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
682
683 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
684 padconf |= mask;
685 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
686
687 /* reset modem */
666 OMAP3430_RST2_IVA2_MASK |
667 OMAP3430_RST3_IVA2_MASK,
668 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
669}
670
671static void __init omap3_d2d_idle(void)
672{
673 u16 mask, padconf;

--- 7 unchanged lines hidden (view full) ---

681 padconf |= mask;
682 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
683
684 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
685 padconf |= mask;
686 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
687
688 /* reset modem */
688 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
689 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
689 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
690 CORE_MOD, OMAP2_RM_RSTCTRL);
690 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
691 CORE_MOD, OMAP2_RM_RSTCTRL);
691 prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
692 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
692}
693
694static void __init prcm_setup_regs(void)
695{
696 u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
697 OMAP3630_AUTO_UART4_MASK : 0;
698 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
699 OMAP3630_EN_UART4_MASK : 0;
700 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
701 OMAP3630_GRPSEL_UART4_MASK : 0;
702
703
704 /* XXX Reset all wkdeps. This should be done when initializing
705 * powerdomains */
693}
694
695static void __init prcm_setup_regs(void)
696{
697 u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
698 OMAP3630_AUTO_UART4_MASK : 0;
699 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
700 OMAP3630_EN_UART4_MASK : 0;
701 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
702 OMAP3630_GRPSEL_UART4_MASK : 0;
703
704
705 /* XXX Reset all wkdeps. This should be done when initializing
706 * powerdomains */
706 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
707 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
708 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
709 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
710 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
711 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
707 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
708 omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
709 omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
710 omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
711 omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
712 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
712 if (omap_rev() > OMAP3430_REV_ES1_0) {
713 if (omap_rev() > OMAP3430_REV_ES1_0) {
713 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
714 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
714 omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
715 omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
715 } else
716 } else
716 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
717 omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
717
718 /*
719 * Enable interface clock autoidle for all modules.
720 * Note that in the long run this should be done by clockfw
721 */
718
719 /*
720 * Enable interface clock autoidle for all modules.
721 * Note that in the long run this should be done by clockfw
722 */
722 cm_write_mod_reg(
723 omap2_cm_write_mod_reg(
723 OMAP3430_AUTO_MODEM_MASK |
724 OMAP3430ES2_AUTO_MMC3_MASK |
725 OMAP3430ES2_AUTO_ICR_MASK |
726 OMAP3430_AUTO_AES2_MASK |
727 OMAP3430_AUTO_SHA12_MASK |
728 OMAP3430_AUTO_DES2_MASK |
729 OMAP3430_AUTO_MMC2_MASK |
730 OMAP3430_AUTO_MMC1_MASK |

--- 16 unchanged lines hidden (view full) ---

747 OMAP3430_AUTO_MAILBOXES_MASK |
748 OMAP3430_AUTO_OMAPCTRL_MASK |
749 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
750 OMAP3430_AUTO_HSOTGUSB_MASK |
751 OMAP3430_AUTO_SAD2D_MASK |
752 OMAP3430_AUTO_SSI_MASK,
753 CORE_MOD, CM_AUTOIDLE1);
754
724 OMAP3430_AUTO_MODEM_MASK |
725 OMAP3430ES2_AUTO_MMC3_MASK |
726 OMAP3430ES2_AUTO_ICR_MASK |
727 OMAP3430_AUTO_AES2_MASK |
728 OMAP3430_AUTO_SHA12_MASK |
729 OMAP3430_AUTO_DES2_MASK |
730 OMAP3430_AUTO_MMC2_MASK |
731 OMAP3430_AUTO_MMC1_MASK |

--- 16 unchanged lines hidden (view full) ---

748 OMAP3430_AUTO_MAILBOXES_MASK |
749 OMAP3430_AUTO_OMAPCTRL_MASK |
750 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
751 OMAP3430_AUTO_HSOTGUSB_MASK |
752 OMAP3430_AUTO_SAD2D_MASK |
753 OMAP3430_AUTO_SSI_MASK,
754 CORE_MOD, CM_AUTOIDLE1);
755
755 cm_write_mod_reg(
756 omap2_cm_write_mod_reg(
756 OMAP3430_AUTO_PKA_MASK |
757 OMAP3430_AUTO_AES1_MASK |
758 OMAP3430_AUTO_RNG_MASK |
759 OMAP3430_AUTO_SHA11_MASK |
760 OMAP3430_AUTO_DES1_MASK,
761 CORE_MOD, CM_AUTOIDLE2);
762
763 if (omap_rev() > OMAP3430_REV_ES1_0) {
757 OMAP3430_AUTO_PKA_MASK |
758 OMAP3430_AUTO_AES1_MASK |
759 OMAP3430_AUTO_RNG_MASK |
760 OMAP3430_AUTO_SHA11_MASK |
761 OMAP3430_AUTO_DES1_MASK,
762 CORE_MOD, CM_AUTOIDLE2);
763
764 if (omap_rev() > OMAP3430_REV_ES1_0) {
764 cm_write_mod_reg(
765 omap2_cm_write_mod_reg(
765 OMAP3430_AUTO_MAD2D_MASK |
766 OMAP3430ES2_AUTO_USBTLL_MASK,
767 CORE_MOD, CM_AUTOIDLE3);
768 }
769
766 OMAP3430_AUTO_MAD2D_MASK |
767 OMAP3430ES2_AUTO_USBTLL_MASK,
768 CORE_MOD, CM_AUTOIDLE3);
769 }
770
770 cm_write_mod_reg(
771 omap2_cm_write_mod_reg(
771 OMAP3430_AUTO_WDT2_MASK |
772 OMAP3430_AUTO_WDT1_MASK |
773 OMAP3430_AUTO_GPIO1_MASK |
774 OMAP3430_AUTO_32KSYNC_MASK |
775 OMAP3430_AUTO_GPT12_MASK |
776 OMAP3430_AUTO_GPT1_MASK,
777 WKUP_MOD, CM_AUTOIDLE);
778
772 OMAP3430_AUTO_WDT2_MASK |
773 OMAP3430_AUTO_WDT1_MASK |
774 OMAP3430_AUTO_GPIO1_MASK |
775 OMAP3430_AUTO_32KSYNC_MASK |
776 OMAP3430_AUTO_GPT12_MASK |
777 OMAP3430_AUTO_GPT1_MASK,
778 WKUP_MOD, CM_AUTOIDLE);
779
779 cm_write_mod_reg(
780 omap2_cm_write_mod_reg(
780 OMAP3430_AUTO_DSS_MASK,
781 OMAP3430_DSS_MOD,
782 CM_AUTOIDLE);
783
781 OMAP3430_AUTO_DSS_MASK,
782 OMAP3430_DSS_MOD,
783 CM_AUTOIDLE);
784
784 cm_write_mod_reg(
785 omap2_cm_write_mod_reg(
785 OMAP3430_AUTO_CAM_MASK,
786 OMAP3430_CAM_MOD,
787 CM_AUTOIDLE);
788
786 OMAP3430_AUTO_CAM_MASK,
787 OMAP3430_CAM_MOD,
788 CM_AUTOIDLE);
789
789 cm_write_mod_reg(
790 omap2_cm_write_mod_reg(
790 omap3630_auto_uart4_mask |
791 OMAP3430_AUTO_GPIO6_MASK |
792 OMAP3430_AUTO_GPIO5_MASK |
793 OMAP3430_AUTO_GPIO4_MASK |
794 OMAP3430_AUTO_GPIO3_MASK |
795 OMAP3430_AUTO_GPIO2_MASK |
796 OMAP3430_AUTO_WDT3_MASK |
797 OMAP3430_AUTO_UART3_MASK |

--- 7 unchanged lines hidden (view full) ---

805 OMAP3430_AUTO_GPT2_MASK |
806 OMAP3430_AUTO_MCBSP4_MASK |
807 OMAP3430_AUTO_MCBSP3_MASK |
808 OMAP3430_AUTO_MCBSP2_MASK,
809 OMAP3430_PER_MOD,
810 CM_AUTOIDLE);
811
812 if (omap_rev() > OMAP3430_REV_ES1_0) {
791 omap3630_auto_uart4_mask |
792 OMAP3430_AUTO_GPIO6_MASK |
793 OMAP3430_AUTO_GPIO5_MASK |
794 OMAP3430_AUTO_GPIO4_MASK |
795 OMAP3430_AUTO_GPIO3_MASK |
796 OMAP3430_AUTO_GPIO2_MASK |
797 OMAP3430_AUTO_WDT3_MASK |
798 OMAP3430_AUTO_UART3_MASK |

--- 7 unchanged lines hidden (view full) ---

806 OMAP3430_AUTO_GPT2_MASK |
807 OMAP3430_AUTO_MCBSP4_MASK |
808 OMAP3430_AUTO_MCBSP3_MASK |
809 OMAP3430_AUTO_MCBSP2_MASK,
810 OMAP3430_PER_MOD,
811 CM_AUTOIDLE);
812
813 if (omap_rev() > OMAP3430_REV_ES1_0) {
813 cm_write_mod_reg(
814 omap2_cm_write_mod_reg(
814 OMAP3430ES2_AUTO_USBHOST_MASK,
815 OMAP3430ES2_USBHOST_MOD,
816 CM_AUTOIDLE);
817 }
818
819 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
820
821 /*
822 * Set all plls to autoidle. This is needed until autoidle is
823 * enabled by clockfw
824 */
815 OMAP3430ES2_AUTO_USBHOST_MASK,
816 OMAP3430ES2_USBHOST_MOD,
817 CM_AUTOIDLE);
818 }
819
820 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
821
822 /*
823 * Set all plls to autoidle. This is needed until autoidle is
824 * enabled by clockfw
825 */
825 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
826 omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
826 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
827 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
827 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
828 omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
828 MPU_MOD,
829 CM_AUTOIDLE2);
829 MPU_MOD,
830 CM_AUTOIDLE2);
830 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
831 omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
831 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
832 PLL_MOD,
833 CM_AUTOIDLE);
832 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
833 PLL_MOD,
834 CM_AUTOIDLE);
834 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
835 omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
835 PLL_MOD,
836 CM_AUTOIDLE2);
837
838 /*
839 * Enable control of expternal oscillator through
840 * sys_clkreq. In the long run clock framework should
841 * take care of this.
842 */
836 PLL_MOD,
837 CM_AUTOIDLE2);
838
839 /*
840 * Enable control of expternal oscillator through
841 * sys_clkreq. In the long run clock framework should
842 * take care of this.
843 */
843 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
844 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
844 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
845 OMAP3430_GR_MOD,
846 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
847
848 /* setup wakup source */
845 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
846 OMAP3430_GR_MOD,
847 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
848
849 /* setup wakup source */
849 prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
850 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
850 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
851 WKUP_MOD, PM_WKEN);
852 /* No need to write EN_IO, that is always enabled */
851 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
852 WKUP_MOD, PM_WKEN);
853 /* No need to write EN_IO, that is always enabled */
853 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
854 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
854 OMAP3430_GRPSEL_GPT1_MASK |
855 OMAP3430_GRPSEL_GPT12_MASK,
856 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
857 /* For some reason IO doesn't generate wakeup event even if
858 * it is selected to mpu wakeup goup */
855 OMAP3430_GRPSEL_GPT1_MASK |
856 OMAP3430_GRPSEL_GPT12_MASK,
857 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
858 /* For some reason IO doesn't generate wakeup event even if
859 * it is selected to mpu wakeup goup */
859 prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
860 omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
860 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
861
862 /* Enable PM_WKEN to support DSS LPR */
861 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
862
863 /* Enable PM_WKEN to support DSS LPR */
863 prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
864 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
864 OMAP3430_DSS_MOD, PM_WKEN);
865
866 /* Enable wakeups in PER */
865 OMAP3430_DSS_MOD, PM_WKEN);
866
867 /* Enable wakeups in PER */
867 prm_write_mod_reg(omap3630_en_uart4_mask |
868 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
868 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
869 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
870 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
871 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
872 OMAP3430_EN_MCBSP4_MASK,
873 OMAP3430_PER_MOD, PM_WKEN);
874 /* and allow them to wake up MPU */
869 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
870 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
871 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
872 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
873 OMAP3430_EN_MCBSP4_MASK,
874 OMAP3430_PER_MOD, PM_WKEN);
875 /* and allow them to wake up MPU */
875 prm_write_mod_reg(omap3630_grpsel_uart4_mask |
876 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
876 OMAP3430_GRPSEL_GPIO2_MASK |
877 OMAP3430_GRPSEL_GPIO3_MASK |
878 OMAP3430_GRPSEL_GPIO4_MASK |
879 OMAP3430_GRPSEL_GPIO5_MASK |
880 OMAP3430_GRPSEL_GPIO6_MASK |
881 OMAP3430_GRPSEL_UART3_MASK |
882 OMAP3430_GRPSEL_MCBSP2_MASK |
883 OMAP3430_GRPSEL_MCBSP3_MASK |
884 OMAP3430_GRPSEL_MCBSP4_MASK,
885 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
886
887 /* Don't attach IVA interrupts */
877 OMAP3430_GRPSEL_GPIO2_MASK |
878 OMAP3430_GRPSEL_GPIO3_MASK |
879 OMAP3430_GRPSEL_GPIO4_MASK |
880 OMAP3430_GRPSEL_GPIO5_MASK |
881 OMAP3430_GRPSEL_GPIO6_MASK |
882 OMAP3430_GRPSEL_UART3_MASK |
883 OMAP3430_GRPSEL_MCBSP2_MASK |
884 OMAP3430_GRPSEL_MCBSP3_MASK |
885 OMAP3430_GRPSEL_MCBSP4_MASK,
886 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
887
888 /* Don't attach IVA interrupts */
888 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
889 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
890 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
891 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
889 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
890 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
891 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
892 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
892
893 /* Clear any pending 'reset' flags */
893
894 /* Clear any pending 'reset' flags */
894 prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
895 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
896 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
897 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
898 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
899 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
900 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
895 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
896 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
897 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
898 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
899 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
900 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
901 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
901
902 /* Clear any pending PRCM interrupts */
902
903 /* Clear any pending PRCM interrupts */
903 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
904 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
904
905 omap3_iva_idle();
906 omap3_d2d_idle();
907}
908
909void omap3_pm_off_mode_enable(int enable)
910{
911 struct power_state *pwrst;

--- 211 unchanged lines hidden --- 		905
906 omap3_iva_idle();
907 omap3_d2d_idle();
908}
909
910void omap3_pm_off_mode_enable(int enable)
911{
912 struct power_state *pwrst;

--- 211 unchanged lines hidden ---