pm34xx.c (076f2cc449188b7d3d4866730afa3ac7be3e6640) pm34xx.c (2c74a0cefa463a7a483b07ba4d2ea8e4ec7b996c)
1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.

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26#include <linux/err.h>
27#include <linux/gpio.h>
28#include <linux/clk.h>
29#include <linux/delay.h>
30#include <linux/slab.h>
31#include <linux/console.h>
32#include <trace/events/power.h>
33
1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
8 * Copyright (C) 2007 Texas Instruments, Inc.

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26#include <linux/err.h>
27#include <linux/gpio.h>
28#include <linux/clk.h>
29#include <linux/delay.h>
30#include <linux/slab.h>
31#include <linux/console.h>
32#include <trace/events/power.h>
33
34#include <asm/suspend.h>
35
34#include <plat/sram.h>
35#include "clockdomain.h"
36#include "powerdomain.h"
37#include <plat/serial.h>
38#include <plat/sdrc.h>
39#include <plat/prcm.h>
40#include <plat/gpmc.h>
41#include <plat/dma.h>

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406 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
407
408 /*
409 * omap3_arm_context is the location where some ARM context
410 * get saved. The rest is placed on the stack, and restored
411 * from there before resuming.
412 */
413 if (save_state == 1 || save_state == 3)
36#include <plat/sram.h>
37#include "clockdomain.h"
38#include "powerdomain.h"
39#include <plat/serial.h>
40#include <plat/sdrc.h>
41#include <plat/prcm.h>
42#include <plat/gpmc.h>
43#include <plat/dma.h>

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408 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
409
410 /*
411 * omap3_arm_context is the location where some ARM context
412 * get saved. The rest is placed on the stack, and restored
413 * from there before resuming.
414 */
415 if (save_state == 1 || save_state == 3)
414 cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, save_state,
415 omap34xx_do_sram_idle);
416 cpu_suspend(save_state, omap34xx_do_sram_idle);
416 else
417 omap34xx_do_sram_idle(save_state);
418
419 /* Restore normal SDRC POWER settings */
420 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
421 omap_type() != OMAP2_DEVICE_TYPE_GP &&
422 core_next_state == PWRDM_POWER_OFF)
423 sdrc_write_reg(sdrc_pwr, SDRC_POWER);

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418 omap34xx_do_sram_idle(save_state);
419
420 /* Restore normal SDRC POWER settings */
421 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
422 omap_type() != OMAP2_DEVICE_TYPE_GP &&
423 core_next_state == PWRDM_POWER_OFF)
424 sdrc_write_reg(sdrc_pwr, SDRC_POWER);

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