io.c (d905163c5b23f6d8511971e06081a1b525e8a0bd) io.c (2f135eaf182761bb9a5cbd5138a447b0ad2a1fef)
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *

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16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/io.h>
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *

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16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/clk.h>
24
25#include <asm/tlb.h>
26
27#include <asm/mach/map.h>
28
29#include <mach/mux.h>
30#include <mach/omapfb.h>
31#include <mach/sram.h>

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236 local_flush_tlb_all();
237 flush_cache_all();
238
239 omap2_check_revision();
240 omap_sram_init();
241 omapfb_reserve_sdram();
242}
243
25
26#include <asm/tlb.h>
27
28#include <asm/mach/map.h>
29
30#include <mach/mux.h>
31#include <mach/omapfb.h>
32#include <mach/sram.h>

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237 local_flush_tlb_all();
238 flush_cache_all();
239
240 omap2_check_revision();
241 omap_sram_init();
242 omapfb_reserve_sdram();
243}
244
245/*
246 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
247 *
248 * Sets the CORE DPLL3 M2 divider to the same value that it's at
249 * currently. This has the effect of setting the SDRC SDRAM AC timing
250 * registers to the values currently defined by the kernel. Currently
251 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
252 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
253 * or passes along the return value of clk_set_rate().
254 */
255static int __init _omap2_init_reprogram_sdrc(void)
256{
257 struct clk *dpll3_m2_ck;
258 int v = -EINVAL;
259 long rate;
260
261 if (!cpu_is_omap34xx())
262 return 0;
263
264 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
265 if (!dpll3_m2_ck)
266 return -EINVAL;
267
268 rate = clk_get_rate(dpll3_m2_ck);
269 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
270 v = clk_set_rate(dpll3_m2_ck, rate);
271 if (v)
272 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
273
274 clk_put(dpll3_m2_ck);
275
276 return v;
277}
278
244void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
245{
246 omap2_mux_init();
247#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
248 pwrdm_init(powerdomains_omap);
249 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
250 omap2_clk_init();
251 omap2_sdrc_init(sp);
279void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
280{
281 omap2_mux_init();
282#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
283 pwrdm_init(powerdomains_omap);
284 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
285 omap2_clk_init();
286 omap2_sdrc_init(sp);
287 _omap2_init_reprogram_sdrc();
252#endif
253 gpmc_init();
254}
288#endif
289 gpmc_init();
290}