io.c (cb54b53adae70701bdd77d848cea4b9b39b61cf9) io.c (a3a9384a115756e275ed3845b5f92f21efd5a691)
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *

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246 .length = PAGE_SIZE,
247 .type = MT_MEMORY_SO,
248 },
249#endif
250
251};
252#endif
253
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *

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246 .length = PAGE_SIZE,
247 .type = MT_MEMORY_SO,
248 },
249#endif
250
251};
252#endif
253
254#ifdef CONFIG_SOC_OMAP5
254#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
255static struct map_desc omap54xx_io_desc[] __initdata = {
256 {
257 .virtual = L3_54XX_VIRT,
258 .pfn = __phys_to_pfn(L3_54XX_PHYS),
259 .length = L3_54XX_SIZE,
260 .type = MT_DEVICE,
261 },
262 {

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328#ifdef CONFIG_ARCH_OMAP4
329void __init omap4_map_io(void)
330{
331 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
332 omap_barriers_init();
333}
334#endif
335
255static struct map_desc omap54xx_io_desc[] __initdata = {
256 {
257 .virtual = L3_54XX_VIRT,
258 .pfn = __phys_to_pfn(L3_54XX_PHYS),
259 .length = L3_54XX_SIZE,
260 .type = MT_DEVICE,
261 },
262 {

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328#ifdef CONFIG_ARCH_OMAP4
329void __init omap4_map_io(void)
330{
331 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
332 omap_barriers_init();
333}
334#endif
335
336#ifdef CONFIG_SOC_OMAP5
336#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
337void __init omap5_map_io(void)
338{
339 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
340 omap_barriers_init();
341}
342#endif
343/*
344 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters

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648 omap54xx_voltagedomains_init();
649 omap54xx_powerdomains_init();
650 omap54xx_clockdomains_init();
651 omap54xx_hwmod_init();
652 omap_hwmod_init_postsetup();
653}
654#endif
655
337void __init omap5_map_io(void)
338{
339 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
340 omap_barriers_init();
341}
342#endif
343/*
344 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters

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648 omap54xx_voltagedomains_init();
649 omap54xx_powerdomains_init();
650 omap54xx_clockdomains_init();
651 omap54xx_hwmod_init();
652 omap_hwmod_init_postsetup();
653}
654#endif
655
656#ifdef CONFIG_SOC_DRA7XX
657void __init dra7xx_init_early(void)
658{
659 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
660 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
661 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
662 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
663 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
664 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
665 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
666 omap_prm_base_init();
667 omap_cm_base_init();
668}
669#endif
670
671
656void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
657 struct omap_sdrc_params *sdrc_cs1)
658{
659 omap_sram_init();
660
661 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
662 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
663 _omap2_init_reprogram_sdrc();
664 }
665}
672void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
673 struct omap_sdrc_params *sdrc_cs1)
674{
675 omap_sram_init();
676
677 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
678 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
679 _omap2_init_reprogram_sdrc();
680 }
681}