io.c (456e8d53482537616899a146b706eccd095404e6) io.c (ec490f6f600f93236f1ad439b9809de563343b2c)
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *

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363 omap_barriers_init();
364}
365#endif
366
367#ifdef CONFIG_SOC_DRA7XX
368void __init dra7xx_map_io(void)
369{
370 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *

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363 omap_barriers_init();
364}
365#endif
366
367#ifdef CONFIG_SOC_DRA7XX
368void __init dra7xx_map_io(void)
369{
370 iotable_init(dra7xx_io_desc, ARRAY_SIZE(dra7xx_io_desc));
371 omap_barriers_init();
372}
373#endif
374/*
375 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
376 *
377 * Sets the CORE DPLL3 M2 divider to the same value that it's at
378 * currently. This has the effect of setting the SDRC SDRAM AC timing
379 * registers to the values currently defined by the kernel. Currently

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732 omap4_pm_init();
733 omap2_clk_enable_autoidle_all();
734}
735#endif
736
737#ifdef CONFIG_SOC_DRA7XX
738void __init dra7xx_init_early(void)
739{
371}
372#endif
373/*
374 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
375 *
376 * Sets the CORE DPLL3 M2 divider to the same value that it's at
377 * currently. This has the effect of setting the SDRC SDRAM AC timing
378 * registers to the values currently defined by the kernel. Currently

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731 omap4_pm_init();
732 omap2_clk_enable_autoidle_all();
733}
734#endif
735
736#ifdef CONFIG_SOC_DRA7XX
737void __init dra7xx_init_early(void)
738{
740 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
739 omap2_set_globals_tap(DRA7XX_CLASS,
740 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
741 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
742 omap2_control_base_init();
743 omap4_pm_init_early();
744 omap2_prcm_base_init();
745 dra7xxx_check_revision();
746 dra7xx_powerdomains_init();
747 dra7xx_clockdomains_init();
748 dra7xx_hwmod_init();

--- 55 unchanged lines hidden --- 		741 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
742 omap2_control_base_init();
743 omap4_pm_init_early();
744 omap2_prcm_base_init();
745 dra7xxx_check_revision();
746 dra7xx_powerdomains_init();
747 dra7xx_clockdomains_init();
748 dra7xx_hwmod_init();

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