io.c (1348bbf942ebf21db7ff235f9bbdf9cd36be3ffe) io.c (ff931c821bab6713a52b768b0cd7ee7e90713b36)
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *

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50#include "prcm_mpu44xx.h"
51#include "prminst44xx.h"
52#include "cminst44xx.h"
53#include "prm2xxx.h"
54#include "prm3xxx.h"
55#include "prm44xx.h"
56
57/*
1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
8 *

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50#include "prcm_mpu44xx.h"
51#include "prminst44xx.h"
52#include "cminst44xx.h"
53#include "prm2xxx.h"
54#include "prm3xxx.h"
55#include "prm44xx.h"
56
57/*
58 * omap_clk_init: points to a function that does the SoC-specific
59 * clock initializations
60 */
61int (*omap_clk_init)(void);
62
63/*
58 * The machine specific code may provide the extra mapping besides the
59 * default mapping provided here.
60 */
61
62#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
63static struct map_desc omap24xx_io_desc[] __initdata = {
64 {
65 .virtual = L3_24XX_VIRT,

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266 .type = MT_DEVICE,
267 },
268 {
269 .virtual = L4_PER_54XX_VIRT,
270 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
271 .length = L4_PER_54XX_SIZE,
272 .type = MT_DEVICE,
273 },
64 * The machine specific code may provide the extra mapping besides the
65 * default mapping provided here.
66 */
67
68#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
69static struct map_desc omap24xx_io_desc[] __initdata = {
70 {
71 .virtual = L3_24XX_VIRT,

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272 .type = MT_DEVICE,
273 },
274 {
275 .virtual = L4_PER_54XX_VIRT,
276 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
277 .length = L4_PER_54XX_SIZE,
278 .type = MT_DEVICE,
279 },
274#ifdef CONFIG_OMAP4_ERRATA_I688
275 {
276 .virtual = OMAP4_SRAM_VA,
277 .pfn = __phys_to_pfn(OMAP4_SRAM_PA),
278 .length = PAGE_SIZE,
279 .type = MT_MEMORY_SO,
280 },
281#endif
282};
283#endif
284
285#ifdef CONFIG_SOC_OMAP2420
286void __init omap242x_map_io(void)
287{
288 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
289 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));

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326 omap_barriers_init();
327}
328#endif
329
330#ifdef CONFIG_SOC_OMAP5
331void __init omap5_map_io(void)
332{
333 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
280};
281#endif
282
283#ifdef CONFIG_SOC_OMAP2420
284void __init omap242x_map_io(void)
285{
286 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
287 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));

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324 omap_barriers_init();
325}
326#endif
327
328#ifdef CONFIG_SOC_OMAP5
329void __init omap5_map_io(void)
330{
331 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
334 omap_barriers_init();
335}
336#endif
337/*
338 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
339 *
340 * Sets the CORE DPLL3 M2 divider to the same value that it's at
341 * currently. This has the effect of setting the SDRC SDRAM AC timing
342 * registers to the values currently defined by the kernel. Currently

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401 omap2xxx_check_revision();
402 omap2xxx_prm_init();
403 omap2xxx_cm_init();
404 omap2xxx_voltagedomains_init();
405 omap242x_powerdomains_init();
406 omap242x_clockdomains_init();
407 omap2420_hwmod_init();
408 omap_hwmod_init_postsetup();
332}
333#endif
334/*
335 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
336 *
337 * Sets the CORE DPLL3 M2 divider to the same value that it's at
338 * currently. This has the effect of setting the SDRC SDRAM AC timing
339 * registers to the values currently defined by the kernel. Currently

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398 omap2xxx_check_revision();
399 omap2xxx_prm_init();
400 omap2xxx_cm_init();
401 omap2xxx_voltagedomains_init();
402 omap242x_powerdomains_init();
403 omap242x_clockdomains_init();
404 omap2420_hwmod_init();
405 omap_hwmod_init_postsetup();
409 omap2420_clk_init();
406 omap_clk_init = omap2420_clk_init;
410}
411
412void __init omap2420_init_late(void)
413{
414 omap_mux_late_init();
415 omap2_common_pm_late_init();
416 omap2_pm_init();
417 omap2_clk_enable_autoidle_all();

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431 omap2xxx_check_revision();
432 omap2xxx_prm_init();
433 omap2xxx_cm_init();
434 omap2xxx_voltagedomains_init();
435 omap243x_powerdomains_init();
436 omap243x_clockdomains_init();
437 omap2430_hwmod_init();
438 omap_hwmod_init_postsetup();
407}
408
409void __init omap2420_init_late(void)
410{
411 omap_mux_late_init();
412 omap2_common_pm_late_init();
413 omap2_pm_init();
414 omap2_clk_enable_autoidle_all();

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428 omap2xxx_check_revision();
429 omap2xxx_prm_init();
430 omap2xxx_cm_init();
431 omap2xxx_voltagedomains_init();
432 omap243x_powerdomains_init();
433 omap243x_clockdomains_init();
434 omap2430_hwmod_init();
435 omap_hwmod_init_postsetup();
439 omap2430_clk_init();
436 omap_clk_init = omap2430_clk_init;
440}
441
442void __init omap2430_init_late(void)
443{
444 omap_mux_late_init();
445 omap2_common_pm_late_init();
446 omap2_pm_init();
447 omap2_clk_enable_autoidle_all();

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466 omap3xxx_check_features();
467 omap3xxx_prm_init();
468 omap3xxx_cm_init();
469 omap3xxx_voltagedomains_init();
470 omap3xxx_powerdomains_init();
471 omap3xxx_clockdomains_init();
472 omap3xxx_hwmod_init();
473 omap_hwmod_init_postsetup();
437}
438
439void __init omap2430_init_late(void)
440{
441 omap_mux_late_init();
442 omap2_common_pm_late_init();
443 omap2_pm_init();
444 omap2_clk_enable_autoidle_all();

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463 omap3xxx_check_features();
464 omap3xxx_prm_init();
465 omap3xxx_cm_init();
466 omap3xxx_voltagedomains_init();
467 omap3xxx_powerdomains_init();
468 omap3xxx_clockdomains_init();
469 omap3xxx_hwmod_init();
470 omap_hwmod_init_postsetup();
474 omap3xxx_clk_init();
471 omap_clk_init = omap3xxx_clk_init;
475}
476
477void __init omap3430_init_early(void)
478{
479 omap3_init_early();
480}
481
482void __init omap35xx_init_early(void)

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504 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
505 omap3xxx_check_revision();
506 ti81xx_check_features();
507 omap3xxx_voltagedomains_init();
508 omap3xxx_powerdomains_init();
509 omap3xxx_clockdomains_init();
510 omap3xxx_hwmod_init();
511 omap_hwmod_init_postsetup();
472}
473
474void __init omap3430_init_early(void)
475{
476 omap3_init_early();
477}
478
479void __init omap35xx_init_early(void)

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501 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
502 omap3xxx_check_revision();
503 ti81xx_check_features();
504 omap3xxx_voltagedomains_init();
505 omap3xxx_powerdomains_init();
506 omap3xxx_clockdomains_init();
507 omap3xxx_hwmod_init();
508 omap_hwmod_init_postsetup();
512 omap3xxx_clk_init();
509 omap_clk_init = omap3xxx_clk_init;
513}
514
515void __init omap3_init_late(void)
516{
517 omap_mux_late_init();
518 omap2_common_pm_late_init();
519 omap3_pm_init();
520 omap2_clk_enable_autoidle_all();

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572 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
573 omap3xxx_check_revision();
574 ti81xx_check_features();
575 am33xx_voltagedomains_init();
576 am33xx_powerdomains_init();
577 am33xx_clockdomains_init();
578 am33xx_hwmod_init();
579 omap_hwmod_init_postsetup();
510}
511
512void __init omap3_init_late(void)
513{
514 omap_mux_late_init();
515 omap2_common_pm_late_init();
516 omap3_pm_init();
517 omap2_clk_enable_autoidle_all();

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569 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
570 omap3xxx_check_revision();
571 ti81xx_check_features();
572 am33xx_voltagedomains_init();
573 am33xx_powerdomains_init();
574 am33xx_clockdomains_init();
575 am33xx_hwmod_init();
576 omap_hwmod_init_postsetup();
580 am33xx_clk_init();
577 omap_clk_init = am33xx_clk_init;
581}
582#endif
583
584#ifdef CONFIG_ARCH_OMAP4
585void __init omap4430_init_early(void)
586{
587 omap2_set_globals_tap(OMAP443X_CLASS,
588 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));

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597 omap4xxx_check_revision();
598 omap4xxx_check_features();
599 omap44xx_prm_init();
600 omap44xx_voltagedomains_init();
601 omap44xx_powerdomains_init();
602 omap44xx_clockdomains_init();
603 omap44xx_hwmod_init();
604 omap_hwmod_init_postsetup();
578}
579#endif
580
581#ifdef CONFIG_ARCH_OMAP4
582void __init omap4430_init_early(void)
583{
584 omap2_set_globals_tap(OMAP443X_CLASS,
585 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));

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594 omap4xxx_check_revision();
595 omap4xxx_check_features();
596 omap44xx_prm_init();
597 omap44xx_voltagedomains_init();
598 omap44xx_powerdomains_init();
599 omap44xx_clockdomains_init();
600 omap44xx_hwmod_init();
601 omap_hwmod_init_postsetup();
605 omap4xxx_clk_init();
602 omap_clk_init = omap4xxx_clk_init;
606}
607
608void __init omap4430_init_late(void)
609{
610 omap_mux_late_init();
611 omap2_common_pm_late_init();
612 omap4_pm_init();
613 omap2_clk_enable_autoidle_all();

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604
605void __init omap4430_init_late(void)
606{
607 omap_mux_late_init();
608 omap2_common_pm_late_init();
609 omap4_pm_init();
610 omap2_clk_enable_autoidle_all();

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