control.c (4ba25a496f62129a2ad8c2436ab2b402752dc66c) control.c (c6a2d839d0dba8a06f55c7b06f8ce33bdbe4aea3)
1/*
2 * OMAP2/3 System Control Module register access
3 *
4 * Copyright (C) 2007, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *

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41 u32 sdrc_module_semaphore;
42 u32 prcm_block_offset;
43 u32 sdrc_block_offset;
44};
45
46struct omap3_scratchpad_prcm_block {
47 u32 prm_clksrc_ctrl;
48 u32 prm_clksel;
1/*
2 * OMAP2/3 System Control Module register access
3 *
4 * Copyright (C) 2007, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 *

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41 u32 sdrc_module_semaphore;
42 u32 prcm_block_offset;
43 u32 sdrc_block_offset;
44};
45
46struct omap3_scratchpad_prcm_block {
47 u32 prm_clksrc_ctrl;
48 u32 prm_clksel;
49 u32 cm_clksel_core;
50 u32 cm_clksel_wkup;
51 u32 cm_clken_pll;
52 u32 cm_autoidle_pll;
53 u32 cm_clksel1_pll;
54 u32 cm_clksel2_pll;
55 u32 cm_clksel3_pll;
56 u32 cm_clken_pll_mpu;
57 u32 cm_autoidle_pll_mpu;
58 u32 cm_clksel1_pll_mpu;
59 u32 cm_clksel2_pll_mpu;
49 u32 cm_contents[11];
60 u32 prcm_block_size;
61};
62
63struct omap3_scratchpad_sdrc_block {
64 u16 sysconfig;
65 u16 cs_cfg;
66 u16 sharing;
67 u16 err_type;

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342
343 /* Populate the PRCM block contents */
344 prcm_block_contents.prm_clksrc_ctrl =
345 omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
346 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
347 prcm_block_contents.prm_clksel =
348 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
349 OMAP3_PRM_CLKSEL_OFFSET);
50 u32 prcm_block_size;
51};
52
53struct omap3_scratchpad_sdrc_block {
54 u16 sysconfig;
55 u16 cs_cfg;
56 u16 sharing;
57 u16 err_type;

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332
333 /* Populate the PRCM block contents */
334 prcm_block_contents.prm_clksrc_ctrl =
335 omap2_prm_read_mod_reg(OMAP3430_GR_MOD,
336 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
337 prcm_block_contents.prm_clksel =
338 omap2_prm_read_mod_reg(OMAP3430_CCR_MOD,
339 OMAP3_PRM_CLKSEL_OFFSET);
350 prcm_block_contents.cm_clksel_core =
351 omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
352 prcm_block_contents.cm_clksel_wkup =
353 omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
354 prcm_block_contents.cm_clken_pll =
355 omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
356 /*
357 * As per erratum i671, ROM code does not respect the PER DPLL
358 * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
359 * Then, in anycase, clear these bits to avoid extra latencies.
360 */
361 prcm_block_contents.cm_autoidle_pll =
362 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
363 ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
364 prcm_block_contents.cm_clksel1_pll =
365 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
366 prcm_block_contents.cm_clksel2_pll =
367 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
368 prcm_block_contents.cm_clksel3_pll =
369 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
370 prcm_block_contents.cm_clken_pll_mpu =
371 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
372 prcm_block_contents.cm_autoidle_pll_mpu =
373 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
374 prcm_block_contents.cm_clksel1_pll_mpu =
375 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
376 prcm_block_contents.cm_clksel2_pll_mpu =
377 omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
340
341 omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
342
378 prcm_block_contents.prcm_block_size = 0x0;
379
380 /* Populate the SDRC block contents */
381 sdrc_block_contents.sysconfig =
382 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
383 sdrc_block_contents.cs_cfg =
384 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
385 sdrc_block_contents.sharing =

--- 222 unchanged lines hidden --- 		343 prcm_block_contents.prcm_block_size = 0x0;
344
345 /* Populate the SDRC block contents */
346 sdrc_block_contents.sysconfig =
347 (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
348 sdrc_block_contents.cs_cfg =
349 (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
350 sdrc_block_contents.sharing =

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