cm2xxx.c (bf61c8840efe60fd8f91446860b63338fb424158) cm2xxx.c (cd6e9db27728e8bcf98cb667996b121761f58121)
1/*
2 * OMAP2xxx CM module functions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 * Rajendra Nayak <rnayak@ti.com>
8 *

--- 313 unchanged lines hidden (view full) ---

322 .clkdm_sleep = omap2xxx_clkdm_sleep,
323 .clkdm_wakeup = omap2xxx_clkdm_wakeup,
324 .clkdm_allow_idle = omap2xxx_clkdm_allow_idle,
325 .clkdm_deny_idle = omap2xxx_clkdm_deny_idle,
326 .clkdm_clk_enable = omap2xxx_clkdm_clk_enable,
327 .clkdm_clk_disable = omap2xxx_clkdm_clk_disable,
328};
329
1/*
2 * OMAP2xxx CM module functions
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
6 * Paul Walmsley
7 * Rajendra Nayak <rnayak@ti.com>
8 *

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322 .clkdm_sleep = omap2xxx_clkdm_sleep,
323 .clkdm_wakeup = omap2xxx_clkdm_wakeup,
324 .clkdm_allow_idle = omap2xxx_clkdm_allow_idle,
325 .clkdm_deny_idle = omap2xxx_clkdm_deny_idle,
326 .clkdm_clk_enable = omap2xxx_clkdm_clk_enable,
327 .clkdm_clk_disable = omap2xxx_clkdm_clk_disable,
328};
329
330int omap2xxx_cm_fclks_active(void)
331{
332 u32 f1, f2;
333
334 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
335 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
336
337 return (f1 | f2) ? 1 : 0;
338}
339
340int omap2xxx_cm_mpu_retention_allowed(void)
341{
342 u32 l;
343
344 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
345 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
346 if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
347 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
348 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
349 return 0;
350 /* Check for UART3. */
351 l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
352 if (l & OMAP24XX_EN_UART3_MASK)
353 return 0;
354
355 return 1;
356}
357
358u32 omap2xxx_cm_get_core_clk_src(void)
359{
360 u32 v;
361
362 v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
363 v &= OMAP24XX_CORE_CLK_SRC_MASK;
364
365 return v;
366}
367
368u32 omap2xxx_cm_get_core_pll_config(void)
369{
370 return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);
371}
372
373u32 omap2xxx_cm_get_pll_config(void)
374{
375 return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1);
376}
377
378u32 omap2xxx_cm_get_pll_status(void)
379{
380 return omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
381}
382
383void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
384{
385 u32 tmp;
386
387 omap2_cm_write_mod_reg(mpu, MPU_MOD, CM_CLKSEL);
388 omap2_cm_write_mod_reg(dsp, OMAP24XX_DSP_MOD, CM_CLKSEL);
389 omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL);
390 tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
391 OMAP24XX_CLKSEL_DSS2_MASK;
392 omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
393 if (cpu_is_omap2430())
394 omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
395}
396
330/*
331 *
332 */
333
334static struct cm_ll_data omap2xxx_cm_ll_data = {
335 .split_idlest_reg = &omap2xxx_cm_split_idlest_reg,
336 .wait_module_ready = &omap2xxx_cm_wait_module_ready,
337};

--- 19 unchanged lines hidden --- 		397/*
398 *
399 */
400
401static struct cm_ll_data omap2xxx_cm_ll_data = {
402 .split_idlest_reg = &omap2xxx_cm_split_idlest_reg,
403 .wait_module_ready = &omap2xxx_cm_wait_module_ready,
404};

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