clock.h (38fd2c202a3d82bc12430bce5789fa2c2a406f71) clock.h (f38b0dd63f0d0cca753bf0997eefdfb23dcc9518)
1/*
2 * linux/arch/arm/mach-omap2/clock.h
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>

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16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
18
19#include <linux/kernel.h>
20#include <linux/list.h>
21
22#include <linux/clkdev.h>
23#include <linux/clk-provider.h>
1/*
2 * linux/arch/arm/mach-omap2/clock.h
3 *
4 * Copyright (C) 2005-2009 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>

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16#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
17#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
18
19#include <linux/kernel.h>
20#include <linux/list.h>
21
22#include <linux/clkdev.h>
23#include <linux/clk-provider.h>
24#include <linux/clk/ti.h>
24
25struct omap_clk {
26 u16 cpu;
27 struct clk_lookup lk;
28};
29
30#define CLK(dev, con, ck) \
31 { \
32 .lk = { \
33 .dev_id = dev, \
34 .con_id = con, \
35 .clk = ck, \
36 }, \
37 }
38
39struct clockdomain;
25
26struct omap_clk {
27 u16 cpu;
28 struct clk_lookup lk;
29};
30
31#define CLK(dev, con, ck) \
32 { \
33 .lk = { \
34 .dev_id = dev, \
35 .con_id = con, \
36 .clk = ck, \
37 }, \
38 }
39
40struct clockdomain;
40#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
41
42#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
43 static struct clk _name = { \
44 .name = #_name, \
45 .hw = &_name##_hw.hw, \
46 .parent_names = _parent_array_name, \
47 .num_parents = ARRAY_SIZE(_parent_array_name), \
48 .ops = &_clkops_name, \

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173 * A struct clksel is always associated with one or more struct clks
174 * and one or more struct clksel_rates.
175 */
176struct clksel {
177 struct clk *parent;
178 const struct clksel_rate *rates;
179};
180
41
42#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name) \
43 static struct clk _name = { \
44 .name = #_name, \
45 .hw = &_name##_hw.hw, \
46 .parent_names = _parent_array_name, \
47 .num_parents = ARRAY_SIZE(_parent_array_name), \
48 .ops = &_clkops_name, \

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173 * A struct clksel is always associated with one or more struct clks
174 * and one or more struct clksel_rates.
175 */
176struct clksel {
177 struct clk *parent;
178 const struct clksel_rate *rates;
179};
180
181/**
182 * struct dpll_data - DPLL registers and integration data
183 * @mult_div1_reg: register containing the DPLL M and N bitfields
184 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
185 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
186 * @clk_bypass: struct clk pointer to the clock's bypass clock input
187 * @clk_ref: struct clk pointer to the clock's reference clock input
188 * @control_reg: register containing the DPLL mode bitfield
189 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
190 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
191 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
192 * @last_rounded_m4xen: cache of the last M4X result of
193 * omap4_dpll_regm4xen_round_rate()
194 * @last_rounded_lpmode: cache of the last lpmode result of
195 * omap4_dpll_lpmode_recalc()
196 * @max_multiplier: maximum valid non-bypass multiplier value (actual)
197 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
198 * @min_divider: minimum valid non-bypass divider value (actual)
199 * @max_divider: maximum valid non-bypass divider value (actual)
200 * @modes: possible values of @enable_mask
201 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
202 * @idlest_reg: register containing the DPLL idle status bitfield
203 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
204 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
205 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
206 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
207 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
208 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
209 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
210 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
211 * @flags: DPLL type/features (see below)
212 *
213 * Possible values for @flags:
214 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
215 *
216 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
217 *
218 * XXX Some DPLLs have multiple bypass inputs, so it's not technically
219 * correct to only have one @clk_bypass pointer.
220 *
221 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
222 * @last_rounded_n) should be separated from the runtime-fixed fields
223 * and placed into a different structure, so that the runtime-fixed data
224 * can be placed into read-only space.
225 */
226struct dpll_data {
227 void __iomem *mult_div1_reg;
228 u32 mult_mask;
229 u32 div1_mask;
230 struct clk *clk_bypass;
231 struct clk *clk_ref;
232 void __iomem *control_reg;
233 u32 enable_mask;
234 unsigned long last_rounded_rate;
235 u16 last_rounded_m;
236 u8 last_rounded_m4xen;
237 u8 last_rounded_lpmode;
238 u16 max_multiplier;
239 u8 last_rounded_n;
240 u8 min_divider;
241 u16 max_divider;
242 u8 modes;
243 void __iomem *autoidle_reg;
244 void __iomem *idlest_reg;
245 u32 autoidle_mask;
246 u32 freqsel_mask;
247 u32 idlest_mask;
248 u32 dco_mask;
249 u32 sddiv_mask;
250 u32 lpmode_mask;
251 u32 m4xen_mask;
252 u8 auto_recal_bit;
253 u8 recal_en_bit;
254 u8 recal_st_bit;
255 u8 flags;
256};
257
258/*
259 * struct clk.flags possibilities
260 *
261 * XXX document the rest of the clock flags here
262 *
263 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
264 * bits share the same register. This flag allows the
265 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
266 * should be used. This is a temporary solution - a better approach
267 * would be to associate clock type-specific data with the clock,
268 * similar to the struct dpll_data approach.
269 */
270#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
271#define CLOCK_IDLE_CONTROL (1 << 1)
272#define CLOCK_NO_IDLE_PARENT (1 << 2)
273#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
274#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
275#define CLOCK_CLKOUTX2 (1 << 5)
276
277/**
278 * struct clk_hw_omap - OMAP struct clk
279 * @node: list_head connecting this clock into the full clock list
280 * @enable_reg: register to write to enable the clock (see @enable_bit)
281 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
282 * @flags: see "struct clk.flags possibilities" above
283 * @clksel_reg: for clksel clks, register va containing src/divisor select
284 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
285 * @clksel: for clksel clks, pointer to struct clksel for this clock
286 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
287 * @clkdm_name: clockdomain name that this clock is contained in
288 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
289 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
290 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
291 *
292 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
293 * clock code converted to use clksel.
294 *
295 */
296
297struct clk_hw_omap_ops;
298
299struct clk_hw_omap {
300 struct clk_hw hw;
301 struct list_head node;
302 unsigned long fixed_rate;
303 u8 fixed_div;
304 void __iomem *enable_reg;
305 u8 enable_bit;
306 u8 flags;
307 void __iomem *clksel_reg;
308 u32 clksel_mask;
309 const struct clksel *clksel;
310 struct dpll_data *dpll_data;
311 const char *clkdm_name;
312 struct clockdomain *clkdm;
313 const struct clk_hw_omap_ops *ops;
314};
315
316struct clk_hw_omap_ops {
317 void (*find_idlest)(struct clk_hw_omap *oclk,
318 void __iomem **idlest_reg,
319 u8 *idlest_bit, u8 *idlest_val);
320 void (*find_companion)(struct clk_hw_omap *oclk,
321 void __iomem **other_reg,
322 u8 *other_bit);
323 void (*allow_idle)(struct clk_hw_omap *oclk);

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343#define OMAP3XXX_EN_DPLL_LOCKED 0x7
344
345/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
346#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
347#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
348#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
349#define OMAP4XXX_EN_DPLL_LOCKED 0x7
350
181struct clk_hw_omap_ops {
182 void (*find_idlest)(struct clk_hw_omap *oclk,
183 void __iomem **idlest_reg,
184 u8 *idlest_bit, u8 *idlest_val);
185 void (*find_companion)(struct clk_hw_omap *oclk,
186 void __iomem **other_reg,
187 u8 *other_bit);
188 void (*allow_idle)(struct clk_hw_omap *oclk);

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208#define OMAP3XXX_EN_DPLL_LOCKED 0x7
209
210/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
211#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
212#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
213#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
214#define OMAP4XXX_EN_DPLL_LOCKED 0x7
215
351/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
352#define DPLL_LOW_POWER_STOP 0x1
353#define DPLL_LOW_POWER_BYPASS 0x5
354#define DPLL_LOCKED 0x7
355
356/* DPLL Type and DCO Selection Flags */
357#define DPLL_J_TYPE 0x1
358
359long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
360 unsigned long *parent_rate);
361unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
362int omap3_noncore_dpll_enable(struct clk_hw *hw);
363void omap3_noncore_dpll_disable(struct clk_hw *hw);
364int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
365 unsigned long parent_rate);
366u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
367void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
368void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
216u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
217void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
218void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
369unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
370 unsigned long parent_rate);
371int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
372void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
373void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
219int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
220void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
221void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
374unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
375 unsigned long parent_rate);
376long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
377 unsigned long target_rate,
378 unsigned long *parent_rate);
379
222
380void omap2_init_clk_clkdm(struct clk_hw *clk);
381void __init omap2_clk_disable_clkdm_control(void);
382
383/* clkt_clksel.c public functions */
384u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
385 unsigned long target_rate,
386 u32 *new_div);
387u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
388unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
389long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
390 unsigned long *parent_rate);
391int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
392 unsigned long parent_rate);
393int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
394
395/* clkt_iclk.c public functions */
396extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
397extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
398
223void __init omap2_clk_disable_clkdm_control(void);
224
225/* clkt_clksel.c public functions */
226u32 omap2_clksel_round_rate_div(struct clk_hw_omap *clk,
227 unsigned long target_rate,
228 u32 *new_div);
229u8 omap2_clksel_find_parent_index(struct clk_hw *hw);
230unsigned long omap2_clksel_recalc(struct clk_hw *hw, unsigned long parent_rate);
231long omap2_clksel_round_rate(struct clk_hw *hw, unsigned long target_rate,
232 unsigned long *parent_rate);
233int omap2_clksel_set_rate(struct clk_hw *hw, unsigned long rate,
234 unsigned long parent_rate);
235int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
236
237/* clkt_iclk.c public functions */
238extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
239extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
240
399u8 omap2_init_dpll_parent(struct clk_hw *hw);
400unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
401
402int omap2_dflt_clk_enable(struct clk_hw *hw);
403void omap2_dflt_clk_disable(struct clk_hw *hw);
404int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
405void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
406 void __iomem **other_reg,
407 u8 *other_bit);
408void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
409 void __iomem **idlest_reg,
410 u8 *idlest_bit, u8 *idlest_val);
241unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
242
243int omap2_dflt_clk_enable(struct clk_hw *hw);
244void omap2_dflt_clk_disable(struct clk_hw *hw);
245int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
246void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
247 void __iomem **other_reg,
248 u8 *other_bit);
249void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
250 void __iomem **idlest_reg,
251 u8 *idlest_bit, u8 *idlest_val);
411void omap2_init_clk_hw_omap_clocks(struct clk *clk);
412int omap2_clk_enable_autoidle_all(void);
413int omap2_clk_disable_autoidle_all(void);
414int omap2_clk_allow_idle(struct clk *clk);
415int omap2_clk_deny_idle(struct clk *clk);
416void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
417int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
418void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
419 const char *core_ck_name,

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428extern struct clk_functions omap2_clk_functions;
429
430extern const struct clksel_rate gpt_32k_rates[];
431extern const struct clksel_rate gpt_sys_rates[];
432extern const struct clksel_rate gfx_l3_rates[];
433extern const struct clksel_rate dsp_ick_rates[];
434extern struct clk dummy_ck;
435
252int omap2_clk_enable_autoidle_all(void);
253int omap2_clk_disable_autoidle_all(void);
254int omap2_clk_allow_idle(struct clk *clk);
255int omap2_clk_deny_idle(struct clk *clk);
256void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
257int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
258void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
259 const char *core_ck_name,

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268extern struct clk_functions omap2_clk_functions;
269
270extern const struct clksel_rate gpt_32k_rates[];
271extern const struct clksel_rate gpt_sys_rates[];
272extern const struct clksel_rate gfx_l3_rates[];
273extern const struct clksel_rate dsp_ick_rates[];
274extern struct clk dummy_ck;
275
436extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
437extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
438extern const struct clk_hw_omap_ops clkhwops_wait;
276extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
277extern const struct clk_hw_omap_ops clkhwops_wait;
439extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
440extern const struct clk_hw_omap_ops clkhwops_iclk;
441extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
442extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
443extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
444extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
445extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
446extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
447extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;

--- 22 unchanged lines hidden --- 		278extern const struct clk_hw_omap_ops clkhwops_iclk;
279extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
280extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
281extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
282extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
283extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
284extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
285extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;

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