| mv78xx0.h (9938b04472d5c59f8bd8152a548533a8599596a2) | mv78xx0.h (3584be9ec3bfe2c12bcb40da13fa185d237bff7d) |
|---|---|
| 1/* 2 * Generic definitions for Marvell MV78xx0 SoC flavors: 3 * MV781x0 and MV782x0. 4 * 5 * This file is licensed under the terms of the GNU General Public 6 * License version 2. This program is licensed "as is" without any 7 * warranty of any kind, whether express or implied. 8 */ --- 23 unchanged lines hidden (view full) --- 32 * fee00000 f0800000 64K PCIe #0 I/O space 33 * fee10000 f0900000 64K PCIe #1 I/O space 34 * fee20000 f0a00000 64K PCIe #2 I/O space 35 * fee30000 f0b00000 64K PCIe #3 I/O space 36 * fee40000 f0c00000 64K PCIe #4 I/O space 37 * fee50000 f0d00000 64K PCIe #5 I/O space 38 * fee60000 f0e00000 64K PCIe #6 I/O space 39 * fee70000 f0f00000 64K PCIe #7 I/O space | 1/* 2 * Generic definitions for Marvell MV78xx0 SoC flavors: 3 * MV781x0 and MV782x0. 4 * 5 * This file is licensed under the terms of the GNU General Public 6 * License version 2. This program is licensed "as is" without any 7 * warranty of any kind, whether express or implied. 8 */ --- 23 unchanged lines hidden (view full) --- 32 * fee00000 f0800000 64K PCIe #0 I/O space 33 * fee10000 f0900000 64K PCIe #1 I/O space 34 * fee20000 f0a00000 64K PCIe #2 I/O space 35 * fee30000 f0b00000 64K PCIe #3 I/O space 36 * fee40000 f0c00000 64K PCIe #4 I/O space 37 * fee50000 f0d00000 64K PCIe #5 I/O space 38 * fee60000 f0e00000 64K PCIe #6 I/O space 39 * fee70000 f0f00000 64K PCIe #7 I/O space |
| 40 * fd000000 f1000000 1M on-chip peripheral registers | 40 * fec00000 f1000000 1M on-chip peripheral registers |
| 41 */ 42#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 43#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 44#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) 45#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 46#define MV78XX0_CORE_REGS_SIZE SZ_16K 47 48#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) 49#define MV78XX0_PCIE_IO_SIZE SZ_1M 50 51#define MV78XX0_REGS_PHYS_BASE 0xf1000000 | 41 */ 42#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 43#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 44#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000) 45#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 46#define MV78XX0_CORE_REGS_SIZE SZ_16K 47 48#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) 49#define MV78XX0_PCIE_IO_SIZE SZ_1M 50 51#define MV78XX0_REGS_PHYS_BASE 0xf1000000 |
| 52#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000) | 52#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000) |
| 53#define MV78XX0_REGS_SIZE SZ_1M 54 55#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 56#define MV78XX0_PCIE_MEM_SIZE 0x30000000 57 58/* 59 * Core-specific peripheral registers. 60 */ --- 67 unchanged lines hidden --- | 53#define MV78XX0_REGS_SIZE SZ_1M 54 55#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 56#define MV78XX0_PCIE_MEM_SIZE 0x30000000 57 58/* 59 * Core-specific peripheral registers. 60 */ --- 67 unchanged lines hidden --- |