pm.c (7c394e7be4d267c02eaaac8fa197a7c1b023c99b) pm.c (65c9a8530bec45cea1137635b7992bbb417de9de)
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - Power Management support
6 *
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics

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26
27#include <plat/cpu.h>
28#include <plat/pm.h>
29#include <plat/pll.h>
30#include <plat/regs-srom.h>
31
32#include <mach/regs-irq.h>
33#include <mach/regs-clock.h>
1/*
2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - Power Management support
6 *
7 * Based on arch/arm/mach-s3c2410/pm.c
8 * Copyright (c) 2006 Simtec Electronics

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26
27#include <plat/cpu.h>
28#include <plat/pm.h>
29#include <plat/pll.h>
30#include <plat/regs-srom.h>
31
32#include <mach/regs-irq.h>
33#include <mach/regs-clock.h>
34#include <mach/regs-pmu.h>
35#include <mach/pm-core.h>
36
37#include "common.h"
34#include <mach/pm-core.h>
35
36#include "common.h"
37#include "regs-pmu.h"
38
39static const struct sleep_save exynos4_set_clksrc[] = {
40 { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
41 { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
42 { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
43 { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
44 { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
45 { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },

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39static const struct sleep_save exynos4_set_clksrc[] = {
40 { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, },
41 { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, },
42 { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, },
43 { .reg = EXYNOS4_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
44 { .reg = EXYNOS4_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
45 { .reg = EXYNOS4_CLKSRC_MASK_FSYS , .val = 0x01011111, },

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