pcie.c (b74aae9a2074e1caa2e40bf119f3a633f77c94e4) pcie.c (c3c5a2815d0b7ebde157556685a0ef8ffa34b98c)
1/*
2 * arch/arm/mach-dove/pcie.c
3 *
4 * PCIe functions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.

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21#include <plat/addr-map.h>
22#include "common.h"
23
24struct pcie_port {
25 u8 index;
26 u8 root_bus_nr;
27 void __iomem *base;
28 spinlock_t conf_lock;
1/*
2 * arch/arm/mach-dove/pcie.c
3 *
4 * PCIe functions for Marvell Dove 88AP510 SoC
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.

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21#include <plat/addr-map.h>
22#include "common.h"
23
24struct pcie_port {
25 u8 index;
26 u8 root_bus_nr;
27 void __iomem *base;
28 spinlock_t conf_lock;
29 char io_space_name[16];
29 char mem_space_name[16];
30 char mem_space_name[16];
30 struct resource res;
31 struct resource res[2];
31};
32
33static struct pcie_port pcie_port[2];
34static int num_pcie_ports;
35
36
37static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
38{

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47
48 /*
49 * Generic PCIe unit setup.
50 */
51 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
52
53 orion_pcie_setup(pp->base);
54
32};
33
34static struct pcie_port pcie_port[2];
35static int num_pcie_ports;
36
37
38static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
39{

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48
49 /*
50 * Generic PCIe unit setup.
51 */
52 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
53
54 orion_pcie_setup(pp->base);
55
55 if (pp->index == 0)
56 pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
57 else
58 pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
56 /*
57 * IORESOURCE_IO
58 */
59 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
60 "PCIe %d I/O", pp->index);
61 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
62 pp->res[0].name = pp->io_space_name;
63 if (pp->index == 0) {
64 pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
65 pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
66 } else {
67 pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
68 pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
69 }
70 pp->res[0].flags = IORESOURCE_IO;
71 if (request_resource(&ioport_resource, &pp->res[0]))
72 panic("Request PCIe IO resource failed\n");
73 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
59
60 /*
61 * IORESOURCE_MEM
62 */
63 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
64 "PCIe %d MEM", pp->index);
65 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
74
75 /*
76 * IORESOURCE_MEM
77 */
78 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
79 "PCIe %d MEM", pp->index);
80 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
66 pp->res.name = pp->mem_space_name;
81 pp->res[1].name = pp->mem_space_name;
67 if (pp->index == 0) {
82 if (pp->index == 0) {
68 pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
69 pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
83 pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
84 pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
70 } else {
85 } else {
71 pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
72 pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
86 pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
87 pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
73 }
88 }
74 pp->res.flags = IORESOURCE_MEM;
75 if (request_resource(&iomem_resource, &pp->res))
89 pp->res[1].flags = IORESOURCE_MEM;
90 if (request_resource(&iomem_resource, &pp->res[1]))
76 panic("Request PCIe Memory resource failed\n");
91 panic("Request PCIe Memory resource failed\n");
77 pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
92 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
78
79 return 1;
80}
81
82static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
83{
84 /*
85 * Don't go out when trying to access nonexisting devices

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177
178static struct hw_pci dove_pci __initdata = {
179 .nr_controllers = 2,
180 .setup = dove_pcie_setup,
181 .scan = dove_pcie_scan_bus,
182 .map_irq = dove_pcie_map_irq,
183};
184
93
94 return 1;
95}
96
97static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
98{
99 /*
100 * Don't go out when trying to access nonexisting devices

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192
193static struct hw_pci dove_pci __initdata = {
194 .nr_controllers = 2,
195 .setup = dove_pcie_setup,
196 .scan = dove_pcie_scan_bus,
197 .map_irq = dove_pcie_map_irq,
198};
199
185static void __init add_pcie_port(int index, unsigned long base)
200static void __init add_pcie_port(int index, void __iomem *base)
186{
187 printk(KERN_INFO "Dove PCIe port %d: ", index);
188
201{
202 printk(KERN_INFO "Dove PCIe port %d: ", index);
203
189 if (orion_pcie_link_up((void __iomem *)base)) {
204 if (orion_pcie_link_up(base)) {
190 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
191
192 printk(KERN_INFO "link up\n");
193
194 pp->index = index;
195 pp->root_bus_nr = -1;
205 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
206
207 printk(KERN_INFO "link up\n");
208
209 pp->index = index;
210 pp->root_bus_nr = -1;
196 pp->base = (void __iomem *)base;
211 pp->base = base;
197 spin_lock_init(&pp->conf_lock);
212 spin_lock_init(&pp->conf_lock);
198 memset(&pp->res, 0, sizeof(pp->res));
213 memset(pp->res, 0, sizeof(pp->res));
199 } else {
200 printk(KERN_INFO "link down, ignoring\n");
201 }
202}
203
204void __init dove_pcie_init(int init_port0, int init_port1)
205{
206 vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
207
208 if (init_port0)
209 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
210
211 if (init_port1)
212 add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
213
214 pci_common_init(&dove_pci);
215}
214 } else {
215 printk(KERN_INFO "link down, ignoring\n");
216 }
217}
218
219void __init dove_pcie_init(int init_port0, int init_port1)
220{
221 vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
222
223 if (init_port0)
224 add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
225
226 if (init_port1)
227 add_pcie_port(1, DOVE_PCIE1_VIRT_BASE);
228
229 pci_common_init(&dove_pci);
230}