irq.c (5ae8d15f686f93d2ac60a7b16d8ddfbfdfc7c00f) irq.c (c3c5a2815d0b7ebde157556685a0ef8ffa34b98c)
1/*
2 * arch/arm/mach-dove/irq.c
3 *
4 * Dove IRQ handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.

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13#include <linux/irq.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16#include <asm/mach/arch.h>
17#include <plat/irq.h>
18#include <asm/mach/irq.h>
19#include <mach/pm.h>
20#include <mach/bridge-regs.h>
1/*
2 * arch/arm/mach-dove/irq.c
3 *
4 * Dove IRQ handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.

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13#include <linux/irq.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16#include <asm/mach/arch.h>
17#include <plat/irq.h>
18#include <asm/mach/irq.h>
19#include <mach/pm.h>
20#include <mach/bridge-regs.h>
21#include <plat/orion-gpio.h>
22#include "common.h"
23
24static void pmu_irq_mask(struct irq_data *d)
25{
26 int pin = irq_to_pmu(d->irq);
27 u32 u;
28
29 u = readl(PMU_INTERRUPT_MASK);

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95 0,
96 0,
97};
98
99void __init dove_init_irq(void)
100{
101 int i;
102
21#include "common.h"
22
23static void pmu_irq_mask(struct irq_data *d)
24{
25 int pin = irq_to_pmu(d->irq);
26 u32 u;
27
28 u = readl(PMU_INTERRUPT_MASK);

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94 0,
95 0,
96};
97
98void __init dove_init_irq(void)
99{
100 int i;
101
103 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
104 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
102 orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
103 orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
105
106 /*
107 * Initialize gpiolib for GPIOs 0-71.
108 */
104
105 /*
106 * Initialize gpiolib for GPIOs 0-71.
107 */
109 orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0,
108 orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
110 IRQ_DOVE_GPIO_START, gpio0_irqs);
111
109 IRQ_DOVE_GPIO_START, gpio0_irqs);
110
112 orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0,
111 orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
113 IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
114
112 IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
113
115 orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0,
114 orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
116 IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
117
118 /*
119 * Mask and clear PMU interrupts
120 */
121 writel(0, PMU_INTERRUPT_MASK);
122 writel(0, PMU_INTERRUPT_CAUSE);
123
124 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
125 irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
126 irq_set_status_flags(i, IRQ_LEVEL);
127 set_irq_flags(i, IRQF_VALID);
128 }
129 irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
130}
115 IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
116
117 /*
118 * Mask and clear PMU interrupts
119 */
120 writel(0, PMU_INTERRUPT_MASK);
121 writel(0, PMU_INTERRUPT_CAUSE);
122
123 for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
124 irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
125 irq_set_status_flags(i, IRQ_LEVEL);
126 set_irq_flags(i, IRQF_VALID);
127 }
128 irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
129}