dove.h (ce78179ea6e042e2d3af0a1c71c105431ead483a) dove.h (3584be9ec3bfe2c12bcb40da13fa185d237bff7d)
1/*
2 * Generic definitions for Marvell Dove 88AP510 SoC
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8

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13
14/*
15 * Marvell Dove address maps.
16 *
17 * phys virt size
18 * c8000000 fdb00000 1M Cryptographic SRAM
19 * e0000000 @runtime 128M PCIe-0 Memory space
20 * e8000000 @runtime 128M PCIe-1 Memory space
1/*
2 * Generic definitions for Marvell Dove 88AP510 SoC
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8

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13
14/*
15 * Marvell Dove address maps.
16 *
17 * phys virt size
18 * c8000000 fdb00000 1M Cryptographic SRAM
19 * e0000000 @runtime 128M PCIe-0 Memory space
20 * e8000000 @runtime 128M PCIe-1 Memory space
21 * f1000000 fde00000 8M on-chip south-bridge registers
22 * f1800000 fe600000 8M on-chip north-bridge registers
21 * f1000000 fec00000 1M on-chip south-bridge registers
22 * f1800000 fe400000 8M on-chip north-bridge registers
23 * f2000000 fee00000 1M PCIe-0 I/O space
24 * f2100000 fef00000 1M PCIe-1 I/O space
25 */
26
27#define DOVE_CESA_PHYS_BASE 0xc8000000
28#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
29#define DOVE_CESA_SIZE SZ_1M
30

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37#define DOVE_BOOTROM_PHYS_BASE 0xf8000000
38#define DOVE_BOOTROM_SIZE SZ_128M
39
40#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
41#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
42#define DOVE_SCRATCHPAD_SIZE SZ_1M
43
44#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
23 * f2000000 fee00000 1M PCIe-0 I/O space
24 * f2100000 fef00000 1M PCIe-1 I/O space
25 */
26
27#define DOVE_CESA_PHYS_BASE 0xc8000000
28#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
29#define DOVE_CESA_SIZE SZ_1M
30

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37#define DOVE_BOOTROM_PHYS_BASE 0xf8000000
38#define DOVE_BOOTROM_SIZE SZ_128M
39
40#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
41#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
42#define DOVE_SCRATCHPAD_SIZE SZ_1M
43
44#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
45#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
46#define DOVE_SB_REGS_SIZE SZ_8M
45#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000)
46#define DOVE_SB_REGS_SIZE SZ_1M
47
48#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
47
48#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
49#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000)
49#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000)
50#define DOVE_NB_REGS_SIZE SZ_8M
51
52#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
53#define DOVE_PCIE0_IO_BUS_BASE 0x00000000
54#define DOVE_PCIE0_IO_SIZE SZ_64K
55
56#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
57#define DOVE_PCIE1_IO_BUS_BASE 0x00010000

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51
52#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
53#define DOVE_PCIE0_IO_BUS_BASE 0x00000000
54#define DOVE_PCIE0_IO_SIZE SZ_64K
55
56#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
57#define DOVE_PCIE1_IO_BUS_BASE 0x00010000

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