entry-armv.S (99b056443e6fc61b896607434107b825aec1f10c) entry-armv.S (508074607c7b95b24f0adf633fdf606761bb7824)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/kernel/entry-armv.S
4 *
5 * Copyright (C) 1996,1997,1998 Russell King.
6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
7 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 *

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56 mov_l r0, generic_handle_arch_irq
57 bl call_with_stack
581:
59 .endm
60
61 .macro pabt_helper
62 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
63#ifdef MULTI_PABORT
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/kernel/entry-armv.S
4 *
5 * Copyright (C) 1996,1997,1998 Russell King.
6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
7 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 *

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56 mov_l r0, generic_handle_arch_irq
57 bl call_with_stack
581:
59 .endm
60
61 .macro pabt_helper
62 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
63#ifdef MULTI_PABORT
64 ldr ip, .LCprocfns
65 mov lr, pc
66 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
64 ldr_va ip, processor, offset=PROCESSOR_PABT_FUNC
65 bl_r ip
67#else
68 bl CPU_PABORT_HANDLER
69#endif
70 .endm
71
72 .macro dabt_helper
73
74 @
75 @ Call the processor-specific abort handler:
76 @
77 @ r2 - pt_regs
78 @ r4 - aborted context pc
79 @ r5 - aborted context psr
80 @
81 @ The abort handler must return the aborted address in r0, and
82 @ the fault status register in r1. r9 must be preserved.
83 @
84#ifdef MULTI_DABORT
66#else
67 bl CPU_PABORT_HANDLER
68#endif
69 .endm
70
71 .macro dabt_helper
72
73 @
74 @ Call the processor-specific abort handler:
75 @
76 @ r2 - pt_regs
77 @ r4 - aborted context pc
78 @ r5 - aborted context psr
79 @
80 @ The abort handler must return the aborted address in r0, and
81 @ the fault status register in r1. r9 must be preserved.
82 @
83#ifdef MULTI_DABORT
85 ldr ip, .LCprocfns
86 mov lr, pc
87 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
84 ldr_va ip, processor, offset=PROCESSOR_DABT_FUNC
85 bl_r ip
88#else
89 bl CPU_DABORT_HANDLER
90#endif
91 .endm
92
93 .section .entry.text,"ax",%progbits
94
95/*

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297__fiq_svc:
298 svc_entry trace=0
299 mov r0, sp @ struct pt_regs *regs
300 bl handle_fiq_as_nmi
301 svc_exit_via_fiq
302 UNWIND(.fnend )
303ENDPROC(__fiq_svc)
304
86#else
87 bl CPU_DABORT_HANDLER
88#endif
89 .endm
90
91 .section .entry.text,"ax",%progbits
92
93/*

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295__fiq_svc:
296 svc_entry trace=0
297 mov r0, sp @ struct pt_regs *regs
298 bl handle_fiq_as_nmi
299 svc_exit_via_fiq
300 UNWIND(.fnend )
301ENDPROC(__fiq_svc)
302
305 .align 5
306.LCcralign:
307 .word cr_alignment
308#ifdef MULTI_DABORT
309.LCprocfns:
310 .word processor
311#endif
312.LCfp:
313 .word fp_enter
314
315/*
316 * Abort mode handlers
317 */
318
319@
320@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
321@ and reuses the same macros. However in abort mode we must also
322@ save/restore lr_abt and spsr_abt to make nested aborts safe.

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365 .macro usr_entry, trace=1, uaccess=1
366 UNWIND(.fnstart )
367 UNWIND(.cantunwind ) @ don't unwind the user space
368 sub sp, sp, #PT_REGS_SIZE
369 ARM( stmib sp, {r1 - r12} )
370 THUMB( stmia sp, {r0 - r12} )
371
372 ATRAP( mrc p15, 0, r7, c1, c0, 0)
303/*
304 * Abort mode handlers
305 */
306
307@
308@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
309@ and reuses the same macros. However in abort mode we must also
310@ save/restore lr_abt and spsr_abt to make nested aborts safe.

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353 .macro usr_entry, trace=1, uaccess=1
354 UNWIND(.fnstart )
355 UNWIND(.cantunwind ) @ don't unwind the user space
356 sub sp, sp, #PT_REGS_SIZE
357 ARM( stmib sp, {r1 - r12} )
358 THUMB( stmia sp, {r0 - r12} )
359
360 ATRAP( mrc p15, 0, r7, c1, c0, 0)
373 ATRAP( ldr r8, .LCcralign)
361 ATRAP( ldr_va r8, cr_alignment)
374
375 ldmia r0, {r3 - r5}
376 add r0, sp, #S_PC @ here for interlock avoidance
377 mov r6, #-1 @ "" "" "" ""
378
379 str r3, [sp] @ save the "real" r0 copied
380 @ from the exception stack
381
362
363 ldmia r0, {r3 - r5}
364 add r0, sp, #S_PC @ here for interlock avoidance
365 mov r6, #-1 @ "" "" "" ""
366
367 str r3, [sp] @ save the "real" r0 copied
368 @ from the exception stack
369
382 ATRAP( ldr r8, [r8, #0])
383
384 @
385 @ We are now ready to fill in the remaining blanks on the stack:
386 @
387 @ r4 - lr_<exception>, already fixed up for correct return/restart
388 @ r5 - spsr_<exception>
389 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
390 @
391 @ Also, separately save sp_usr and lr_usr

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500/*
501 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
502 * can never be supported in a single kernel, this code is not applicable at
503 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
504 * made about .arch directives.
505 */
506#if __LINUX_ARM_ARCH__ < 7
507/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
370 @
371 @ We are now ready to fill in the remaining blanks on the stack:
372 @
373 @ r4 - lr_<exception>, already fixed up for correct return/restart
374 @ r5 - spsr_<exception>
375 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
376 @
377 @ Also, separately save sp_usr and lr_usr

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486/*
487 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
488 * can never be supported in a single kernel, this code is not applicable at
489 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
490 * made about .arch directives.
491 */
492#if __LINUX_ARM_ARCH__ < 7
493/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
508#define NEED_CPU_ARCHITECTURE
509 ldr r5, .LCcpu_architecture
510 ldr r5, [r5]
494 ldr_va r5, cpu_architecture
511 cmp r5, #CPU_ARCH_ARMv7
512 blo __und_usr_fault_16 @ 16bit undefined instruction
513/*
514 * The following code won't get run unless the running CPU really is v7, so
515 * coding round the lack of ldrht on older arches is pointless. Temporarily
516 * override the assembler target arch with the minimum required instead:
517 */
518 .arch armv6t2

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649 ret.w lr @ CP#10 (VFP)
650 ret.w lr @ CP#11 (VFP)
651#endif
652 ret.w lr @ CP#12
653 ret.w lr @ CP#13
654 ret.w lr @ CP#14 (Debug)
655 ret.w lr @ CP#15 (Control)
656
495 cmp r5, #CPU_ARCH_ARMv7
496 blo __und_usr_fault_16 @ 16bit undefined instruction
497/*
498 * The following code won't get run unless the running CPU really is v7, so
499 * coding round the lack of ldrht on older arches is pointless. Temporarily
500 * override the assembler target arch with the minimum required instead:
501 */
502 .arch armv6t2

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633 ret.w lr @ CP#10 (VFP)
634 ret.w lr @ CP#11 (VFP)
635#endif
636 ret.w lr @ CP#12
637 ret.w lr @ CP#13
638 ret.w lr @ CP#14 (Debug)
639 ret.w lr @ CP#15 (Control)
640
657#ifdef NEED_CPU_ARCHITECTURE
658 .align 2
659.LCcpu_architecture:
660 .word __cpu_architecture
661#endif
662
663#ifdef CONFIG_NEON
664 .align 6
665
666.LCneon_arm_opcodes:
667 .word 0xfe000000 @ mask
668 .word 0xf2000000 @ opcode
669
670 .word 0xff100000 @ mask

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680 .word 0xff100000 @ mask
681 .word 0xf9000000 @ opcode
682
683 .word 0x00000000 @ mask
684 .word 0x00000000 @ opcode
685#endif
686
687do_fpe:
641#ifdef CONFIG_NEON
642 .align 6
643
644.LCneon_arm_opcodes:
645 .word 0xfe000000 @ mask
646 .word 0xf2000000 @ opcode
647
648 .word 0xff100000 @ mask

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658 .word 0xff100000 @ mask
659 .word 0xf9000000 @ opcode
660
661 .word 0x00000000 @ mask
662 .word 0x00000000 @ opcode
663#endif
664
665do_fpe:
688 ldr r4, .LCfp
689 add r10, r10, #TI_FPSTATE @ r10 = workspace
666 add r10, r10, #TI_FPSTATE @ r10 = workspace
690 ldr pc, [r4] @ Call FP module USR entry point
667 ldr_va pc, fp_enter, tmp=r4 @ Call FP module USR entry point
691
692/*
693 * The FP module is called with these registers set:
694 * r0 = instruction
695 * r2 = PC+4
696 * r9 = normal "successful" return address
697 * r10 = FP workspace
698 * lr = unrecognised FP instruction return address

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669/*
670 * The FP module is called with these registers set:
671 * r0 = instruction
672 * r2 = PC+4
673 * r9 = normal "successful" return address
674 * r10 = FP workspace
675 * lr = unrecognised FP instruction return address

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