| entry-armv.S (5b43e7a383d69381ffe53423e46dd0fafae07da3) | entry-armv.S (19accfd373847ac3d10623c5d20f948846299741) |
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| 1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify --- 930 unchanged lines hidden (view full) --- 939 .globl __kuser_helper_end 940__kuser_helper_end: 941 942 THUMB( .thumb ) 943 944/* 945 * Vector stubs. 946 * | 1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify --- 930 unchanged lines hidden (view full) --- 939 .globl __kuser_helper_end 940__kuser_helper_end: 941 942 THUMB( .thumb ) 943 944/* 945 * Vector stubs. 946 * |
| 947 * This code is copied to 0xffff0200 so we can use branches in the 948 * vectors, rather than ldr's. Note that this code must not 949 * exceed 0x300 bytes. | 947 * This code is copied to 0xffff1000 so we can use branches in the 948 * vectors, rather than ldr's. Note that this code must not exceed 949 * a page size. |
| 950 * 951 * Common stub entry macro: 952 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 953 * 954 * SP points to a minimal amount of processor-private memory, the address 955 * of which is copied into r0 for the mode specific abort handler. 956 */ 957 .macro vector_stub, name, mode, correction=0 --- 32 unchanged lines hidden (view full) --- 990 991 .align 2 992 @ handler addresses follow this label 9931: 994 .endm 995 996 .globl __stubs_start 997__stubs_start: | 950 * 951 * Common stub entry macro: 952 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 953 * 954 * SP points to a minimal amount of processor-private memory, the address 955 * of which is copied into r0 for the mode specific abort handler. 956 */ 957 .macro vector_stub, name, mode, correction=0 --- 32 unchanged lines hidden (view full) --- 990 991 .align 2 992 @ handler addresses follow this label 9931: 994 .endm 995 996 .globl __stubs_start 997__stubs_start: |
| 998 @ This must be the first word 999 .word vector_swi 1000 1001vector_rst: 1002 ARM( swi SYS_ERROR0 ) 1003 THUMB( svc #0 ) 1004 THUMB( nop ) 1005 b vector_und 1006 |
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| 998/* 999 * Interrupt dispatcher 1000 */ 1001 vector_stub irq, IRQ_MODE, 4 1002 1003 .long __irq_usr @ 0 (USR_26 / USR_32) 1004 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1005 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) --- 78 unchanged lines hidden (view full) --- 1084 .long __und_invalid @ c 1085 .long __und_invalid @ d 1086 .long __und_invalid @ e 1087 .long __und_invalid @ f 1088 1089 .align 5 1090 1091/*============================================================================= | 1007/* 1008 * Interrupt dispatcher 1009 */ 1010 vector_stub irq, IRQ_MODE, 4 1011 1012 .long __irq_usr @ 0 (USR_26 / USR_32) 1013 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 1014 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) --- 78 unchanged lines hidden (view full) --- 1093 .long __und_invalid @ c 1094 .long __und_invalid @ d 1095 .long __und_invalid @ e 1096 .long __und_invalid @ f 1097 1098 .align 5 1099 1100/*============================================================================= |
| 1101 * Address exception handler 1102 *----------------------------------------------------------------------------- 1103 * These aren't too critical. 1104 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1105 */ 1106 1107vector_addrexcptn: 1108 b vector_addrexcptn 1109 1110/*============================================================================= |
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| 1092 * Undefined FIQs 1093 *----------------------------------------------------------------------------- 1094 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1095 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1096 * Basically to switch modes, we *HAVE* to clobber one register... brain 1097 * damage alert! I don't think that we can execute any code in here in any 1098 * other mode than FIQ... Ok you can switch to another mode, but you can't 1099 * get out of that mode without clobbering one register. 1100 */ 1101vector_fiq: 1102 subs pc, lr, #4 1103 | 1111 * Undefined FIQs 1112 *----------------------------------------------------------------------------- 1113 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1114 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1115 * Basically to switch modes, we *HAVE* to clobber one register... brain 1116 * damage alert! I don't think that we can execute any code in here in any 1117 * other mode than FIQ... Ok you can switch to another mode, but you can't 1118 * get out of that mode without clobbering one register. 1119 */ 1120vector_fiq: 1121 subs pc, lr, #4 1122 |
| 1104/*============================================================================= 1105 * Address exception handler 1106 *----------------------------------------------------------------------------- 1107 * These aren't too critical. 1108 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1109 */ 1110 1111vector_addrexcptn: 1112 b vector_addrexcptn 1113 1114/* 1115 * We group all the following data together to optimise 1116 * for CPUs with separate I & D caches. 1117 */ 1118 .align 5 1119 1120.LCvswi: 1121 .word vector_swi 1122 | |
| 1123 .globl __stubs_end 1124__stubs_end: 1125 | 1123 .globl __stubs_end 1124__stubs_end: 1125 |
| 1126 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start | 1126 .equ stubs_offset, __vectors_start + 0x1000 - __stubs_start |
| 1127 1128 .globl __vectors_start 1129__vectors_start: | 1127 1128 .globl __vectors_start 1129__vectors_start: |
| 1130 ARM( swi SYS_ERROR0 ) 1131 THUMB( svc #0 ) 1132 THUMB( nop ) | 1130 W(b) vector_rst + stubs_offset |
| 1133 W(b) vector_und + stubs_offset 1134 W(ldr) pc, .LCvswi + stubs_offset 1135 W(b) vector_pabt + stubs_offset 1136 W(b) vector_dabt + stubs_offset 1137 W(b) vector_addrexcptn + stubs_offset 1138 W(b) vector_irq + stubs_offset 1139 W(b) vector_fiq + stubs_offset 1140 --- 17 unchanged lines hidden --- | 1131 W(b) vector_und + stubs_offset 1132 W(ldr) pc, .LCvswi + stubs_offset 1133 W(b) vector_pabt + stubs_offset 1134 W(b) vector_dabt + stubs_offset 1135 W(b) vector_addrexcptn + stubs_offset 1136 W(b) vector_irq + stubs_offset 1137 W(b) vector_fiq + stubs_offset 1138 --- 17 unchanged lines hidden --- |