| entry-armv.S (508074607c7b95b24f0adf633fdf606761bb7824) | entry-armv.S (c4f486f1e7b34b27ec578494a236061b337d50ae) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/arch/arm/kernel/entry-armv.S 4 * 5 * Copyright (C) 1996,1997,1998 Russell King. 6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 7 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 8 * --- 1064 unchanged lines hidden (view full) --- 1073 * Common stub entry macro: 1074 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1075 * 1076 * SP points to a minimal amount of processor-private memory, the address 1077 * of which is copied into r0 for the mode specific abort handler. 1078 */ 1079 .macro vector_stub, name, mode, correction=0 1080 .align 5 | 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/arch/arm/kernel/entry-armv.S 4 * 5 * Copyright (C) 1996,1997,1998 Russell King. 6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 7 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 8 * --- 1064 unchanged lines hidden (view full) --- 1073 * Common stub entry macro: 1074 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1075 * 1076 * SP points to a minimal amount of processor-private memory, the address 1077 * of which is copied into r0 for the mode specific abort handler. 1078 */ 1079 .macro vector_stub, name, mode, correction=0 1080 .align 5 |
| 1081#ifdef CONFIG_HARDEN_BRANCH_HISTORY 1082vector_bhb_bpiall_\name: 1083 mcr p15, 0, r0, c7, c5, 6 @ BPIALL 1084 @ isb not needed due to "movs pc, lr" in the vector stub 1085 @ which gives a "context synchronisation". 1086#endif |
|
| 1081 1082vector_\name: 1083 .if \correction 1084 sub lr, lr, #\correction 1085 .endif 1086 1087 @ Save r0, lr_<exception> (parent PC) 1088 stmia sp, {r0, lr} @ save r0, lr --- 35 unchanged lines hidden (view full) --- 1124 mov r0, #8 11253: W(b) . + 4 1126 subs r0, r0, #1 1127 bne 3b 1128 dsb 1129 isb 1130 b 2b 1131ENDPROC(vector_bhb_loop8_\name) | 1087 1088vector_\name: 1089 .if \correction 1090 sub lr, lr, #\correction 1091 .endif 1092 1093 @ Save r0, lr_<exception> (parent PC) 1094 stmia sp, {r0, lr} @ save r0, lr --- 35 unchanged lines hidden (view full) --- 1130 mov r0, #8 11313: W(b) . + 4 1132 subs r0, r0, #1 1133 bne 3b 1134 dsb 1135 isb 1136 b 2b 1137ENDPROC(vector_bhb_loop8_\name) |
| 1132 1133vector_bhb_bpiall_\name: 1134 .if \correction 1135 sub lr, lr, #\correction 1136 .endif 1137 1138 @ Save r0, lr_<exception> (parent PC) 1139 stmia sp, {r0, lr} 1140 1141 @ bhb workaround 1142 mcr p15, 0, r0, c7, c5, 6 @ BPIALL 1143 @ isb not needed due to "movs pc, lr" in the vector stub 1144 @ which gives a "context synchronisation". 1145 b 2b 1146ENDPROC(vector_bhb_bpiall_\name) | |
| 1147 .previous 1148#endif 1149 1150 .align 2 1151 @ handler addresses follow this label 11521: 1153 .endm 1154 --- 187 unchanged lines hidden --- | 1138 .previous 1139#endif 1140 1141 .align 2 1142 @ handler addresses follow this label 11431: 1144 .endm 1145 --- 187 unchanged lines hidden --- |