| cache.h (498495dba268b20e8eadd7fe93c140c68b6cc9d2) | cache.h (33def8498fdde180023444b08e12b72a9efed41d) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * arch/arm/include/asm/cache.h 4 */ 5#ifndef __ASMARM_CACHE_H 6#define __ASMARM_CACHE_H 7 8#define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT --- 10 unchanged lines hidden (view full) --- 19 20/* 21 * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. 22 */ 23#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 24#define ARCH_SLAB_MINALIGN 8 25#endif 26 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * arch/arm/include/asm/cache.h 4 */ 5#ifndef __ASMARM_CACHE_H 6#define __ASMARM_CACHE_H 7 8#define L1_CACHE_SHIFT CONFIG_ARM_L1_CACHE_SHIFT --- 10 unchanged lines hidden (view full) --- 19 20/* 21 * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. 22 */ 23#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 24#define ARCH_SLAB_MINALIGN 8 25#endif 26 |
| 27#define __read_mostly __attribute__((__section__(".data..read_mostly"))) | 27#define __read_mostly __section(".data..read_mostly") |
| 28 29#endif | 28 29#endif |