| head.S (9a38e989b8ce04923f919fc2a8a24eb07fb484e2) | head.S (28853ac8fe5221de74a14f1182d7b2b383dfd85c) |
|---|---|
| 1/* 2 * linux/arch/arm/boot/compressed/head.S 3 * 4 * Copyright (C) 1996-2002 Russell King 5 * Copyright (C) 2004 Hyok S. Choi (MPU support) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 13 unchanged lines hidden (view full) --- 22#if defined(CONFIG_DEBUG_ICEDCC) 23 24#ifdef CONFIG_CPU_V6 25 .macro loadsp, rb 26 .endm 27 .macro writeb, ch, rb 28 mcr p14, 0, \ch, c0, c5, 0 29 .endm | 1/* 2 * linux/arch/arm/boot/compressed/head.S 3 * 4 * Copyright (C) 1996-2002 Russell King 5 * Copyright (C) 2004 Hyok S. Choi (MPU support) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as --- 13 unchanged lines hidden (view full) --- 22#if defined(CONFIG_DEBUG_ICEDCC) 23 24#ifdef CONFIG_CPU_V6 25 .macro loadsp, rb 26 .endm 27 .macro writeb, ch, rb 28 mcr p14, 0, \ch, c0, c5, 0 29 .endm |
| 30#elif defined(CONFIG_CPU_XSCALE) 31 .macro loadsp, rb 32 .endm 33 .macro writeb, ch, rb 34 mcr p14, 0, \ch, c8, c0, 0 35 .endm | |
| 36#else 37 .macro loadsp, rb 38 .endm 39 .macro writeb, ch, rb 40 mcr p14, 0, \ch, c1, c0, 0 41 .endm 42#endif 43 --- 416 unchanged lines hidden (view full) --- 460 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer 461 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control 462 mcr p15, 0, r0, c1, c0, 0 @ load control register 463 mrc p15, 0, r0, c1, c0, 0 @ and read it back 464 mov r0, #0 465 mcr p15, 0, r0, c7, c5, 4 @ ISB 466 mov pc, r12 467 | 30#else 31 .macro loadsp, rb 32 .endm 33 .macro writeb, ch, rb 34 mcr p14, 0, \ch, c1, c0, 0 35 .endm 36#endif 37 --- 416 unchanged lines hidden (view full) --- 454 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer 455 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control 456 mcr p15, 0, r0, c1, c0, 0 @ load control register 457 mrc p15, 0, r0, c1, c0, 0 @ and read it back 458 mov r0, #0 459 mcr p15, 0, r0, c7, c5, 4 @ ISB 460 mov pc, r12 461 |
| 462__fa526_cache_on: 463 mov r12, lr 464 bl __setup_mmu 465 mov r0, #0 466 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache 467 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 468 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB 469 mrc p15, 0, r0, c1, c0, 0 @ read control reg 470 orr r0, r0, #0x1000 @ I-cache enable 471 bl __common_mmu_cache_on 472 mov r0, #0 473 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB 474 mov pc, r12 475 |
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| 468__arm6_mmu_cache_on: 469 mov r12, lr 470 bl __setup_mmu 471 mov r0, #0 472 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 473 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 474 mov r0, #0x30 475 bl __common_mmu_cache_on --- 155 unchanged lines hidden (view full) --- 631 b __armv4_mmu_cache_flush 632 633 .word 0x56056930 634 .word 0xff0ffff0 @ PXA935 635 b __armv4_mmu_cache_on 636 b __armv4_mmu_cache_off 637 b __armv4_mmu_cache_flush 638 | 476__arm6_mmu_cache_on: 477 mov r12, lr 478 bl __setup_mmu 479 mov r0, #0 480 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 481 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 482 mov r0, #0x30 483 bl __common_mmu_cache_on --- 155 unchanged lines hidden (view full) --- 639 b __armv4_mmu_cache_flush 640 641 .word 0x56056930 642 .word 0xff0ffff0 @ PXA935 643 b __armv4_mmu_cache_on 644 b __armv4_mmu_cache_off 645 b __armv4_mmu_cache_flush 646 |
| 639 .word 0x56158000 @ PXA168 640 .word 0xfffff000 641 b __armv4_mmu_cache_on 642 b __armv4_mmu_cache_off 643 b __armv5tej_mmu_cache_flush 644 645 .word 0x56056930 646 .word 0xff0ffff0 @ PXA935 647 b __armv4_mmu_cache_on 648 b __armv4_mmu_cache_off 649 b __armv4_mmu_cache_flush 650 | |
| 651 .word 0x56050000 @ Feroceon 652 .word 0xff0f0000 653 b __armv4_mmu_cache_on 654 b __armv4_mmu_cache_off 655 b __armv5tej_mmu_cache_flush 656 | 647 .word 0x56050000 @ Feroceon 648 .word 0xff0f0000 649 b __armv4_mmu_cache_on 650 b __armv4_mmu_cache_off 651 b __armv5tej_mmu_cache_flush 652 |
| 653 .word 0x66015261 @ FA526 654 .word 0xff01fff1 655 b __fa526_cache_on 656 b __armv4_mmu_cache_off 657 b __fa526_cache_flush 658 |
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| 657 @ These match on the architecture ID 658 659 .word 0x00020000 @ ARMv4T 660 .word 0x000f0000 661 b __armv4_mmu_cache_on 662 b __armv4_mmu_cache_off 663 b __armv4_mmu_cache_flush 664 --- 123 unchanged lines hidden (view full) --- 788 subs r1, r1, #1 << 5 789 bcs 1b @ segments 7 to 0 790 791 teq r2, #0 792 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 793 mcr p15, 0, ip, c7, c10, 4 @ drain WB 794 mov pc, lr 795 | 659 @ These match on the architecture ID 660 661 .word 0x00020000 @ ARMv4T 662 .word 0x000f0000 663 b __armv4_mmu_cache_on 664 b __armv4_mmu_cache_off 665 b __armv4_mmu_cache_flush 666 --- 123 unchanged lines hidden (view full) --- 790 subs r1, r1, #1 << 5 791 bcs 1b @ segments 7 to 0 792 793 teq r2, #0 794 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 795 mcr p15, 0, ip, c7, c10, 4 @ drain WB 796 mov pc, lr 797 |
| 798__fa526_cache_flush: 799 mov r1, #0 800 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache 801 mcr p15, 0, r1, c7, c5, 0 @ flush I cache 802 mcr p15, 0, r1, c7, c10, 4 @ drain WB 803 mov pc, lr |
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| 796 797__armv6_mmu_cache_flush: 798 mov r1, #0 799 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D 800 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB 801 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified 802 mcr p15, 0, r1, c7, c10, 4 @ drain WB 803 mov pc, lr --- 176 unchanged lines hidden --- | 804 805__armv6_mmu_cache_flush: 806 mov r1, #0 807 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D 808 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB 809 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified 810 mcr p15, 0, r1, c7, c10, 4 @ drain WB 811 mov pc, lr --- 176 unchanged lines hidden --- |