entry.S (c10d6969b0958e151c9dd6cfae70ce8db9db3c7e) entry.S (6d1a20b1d237db29878ae54142e39c87a36d0e95)
1/*
1/*
2 * Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARC
2 * Common Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARC
3 * (included from entry-<isa>.S
3 *
4 *
5 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
6 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
9 *
10 * vineetg: May 2011
11 * -Userspace unaligned access emulation
12 *
13 * vineetg: Feb 2011 (ptrace low level code fixes)
14 * -traced syscall return code (r0) was not saved into pt_regs for restoring
15 * into user reg-file when traded task rets to user space.
16 * -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
17 * were not invoking post-syscall trace hook (jumping directly into
18 * ret_from_system_call)
19 *
20 * vineetg: Nov 2010:
21 * -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
22 * -To maintain the slot size of 8 bytes/vector, added nop, which is
23 * not executed at runtime.
24 *
25 * vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
26 * -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
27 * -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
28 * need ptregs anymore
29 *
30 * Vineetg: Oct 2009
31 * -In a rare scenario, Process gets a Priv-V exception and gets scheduled
32 * out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
33 * active (AE bit enabled). This causes a double fault for a subseq valid
34 * exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
35 * Instr Error could also cause similar scenario, so same there as well.
36 *
37 * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
38 *
39 * Vineetg: Aug 28th 2008: Bug #94984
40 * -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
41 * Normally CPU does this automatically, however when doing FAKE rtie,
42 * we need to explicitly do this. The problem in macros
43 * FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
44 * was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit,
45 * setting it and not clearing it clears ZOL context
46 *
47 * Vineetg: May 16th, 2008
48 * - r25 now contains the Current Task when in kernel
49 *
50 * Vineetg: Dec 22, 2007
51 * Minor Surgery of Low Level ISR to make it SMP safe
52 * - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
53 * - _current_task is made an array of NR_CPUS
54 * - Access of _current_task wrapped inside a macro so that if hardware
55 * team agrees for a dedicated reg, no other code is touched
56 *
57 * Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004
58 */
59
60/*------------------------------------------------------------------
61 * Function ABI
62 *------------------------------------------------------------------
63 *
64 * Arguments r0 - r7
65 * Caller Saved Registers r0 - r12
66 * Callee Saved Registers r13- r25
67 * Global Pointer (gp) r26
68 * Frame Pointer (fp) r27
69 * Stack Pointer (sp) r28
11 */
12
13/*------------------------------------------------------------------
14 * Function ABI
15 *------------------------------------------------------------------
16 *
17 * Arguments r0 - r7
18 * Caller Saved Registers r0 - r12
19 * Callee Saved Registers r13- r25
20 * Global Pointer (gp) r26
21 * Frame Pointer (fp) r27
22 * Stack Pointer (sp) r28
70 * Interrupt link register (ilink1) r29
71 * Interrupt link register (ilink2) r30
72 * Branch link register (blink) r31
73 *------------------------------------------------------------------
74 */
75
23 * Branch link register (blink) r31
24 *------------------------------------------------------------------
25 */
26
76 .cpu A7
77
78;############################ Vector Table #################################
79
80.macro VECTOR lbl
81#if 1 /* Just in case, build breaks */
82 j \lbl
83#else
84 b \lbl
85 nop
86#endif
87.endm
88
89 .section .vector, "ax",@progbits
90 .align 4
91
92/* Each entry in the vector table must occupy 2 words. Since it is a jump
93 * across sections (.vector to .text) we are gauranteed that 'j somewhere'
94 * will use the 'j limm' form of the intrsuction as long as somewhere is in
95 * a section other than .vector.
96 */
97
98; ********* Critical System Events **********************
99VECTOR res_service ; 0x0, Restart Vector (0x0)
100VECTOR mem_service ; 0x8, Mem exception (0x1)
101VECTOR instr_service ; 0x10, Instrn Error (0x2)
102
103; ******************** Device ISRs **********************
104#ifdef CONFIG_ARC_IRQ3_LV2
105VECTOR handle_interrupt_level2
106#else
107VECTOR handle_interrupt_level1
108#endif
109
110VECTOR handle_interrupt_level1
111
112#ifdef CONFIG_ARC_IRQ5_LV2
113VECTOR handle_interrupt_level2
114#else
115VECTOR handle_interrupt_level1
116#endif
117
118#ifdef CONFIG_ARC_IRQ6_LV2
119VECTOR handle_interrupt_level2
120#else
121VECTOR handle_interrupt_level1
122#endif
123
124.rept 25
125VECTOR handle_interrupt_level1 ; Other devices
126.endr
127
128/* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */
129
130; ******************** Exceptions **********************
131VECTOR EV_MachineCheck ; 0x100, Fatal Machine check (0x20)
132VECTOR EV_TLBMissI ; 0x108, Intruction TLB miss (0x21)
133VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22)
134VECTOR EV_TLBProtV ; 0x118, Protection Violation (0x23)
135 ; or Misaligned Access
136VECTOR EV_PrivilegeV ; 0x120, Privilege Violation (0x24)
137VECTOR EV_Trap ; 0x128, Trap exception (0x25)
138VECTOR EV_Extension ; 0x130, Extn Intruction Excp (0x26)
139
140.rept 24
141VECTOR reserved ; Reserved Exceptions
142.endr
143
144#include <linux/linkage.h> /* {EXTRY,EXIT} */
145#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,SYS...} */
146#include <asm/errno.h>
147#include <asm/arcregs.h>
148#include <asm/irqflags.h>
149
150;##################### Scratch Mem for IRQ stack switching #############
151
152ARCFP_DATA int1_saved_reg
153 .align 32
154 .type int1_saved_reg, @object
155 .size int1_saved_reg, 4
156int1_saved_reg:
157 .zero 4
158
159/* Each Interrupt level needs its own scratch */
160#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
161
162ARCFP_DATA int2_saved_reg
163 .type int2_saved_reg, @object
164 .size int2_saved_reg, 4
165int2_saved_reg:
166 .zero 4
167
168#endif
169
170; ---------------------------------------------
171 .section .text, "ax",@progbits
172
173res_service: ; processor restart
174 flag 0x1 ; not implemented
175 nop
176 nop
177
178reserved: ; processor restart
179 rtie ; jump to processor initializations
180
181;##################### Interrupt Handling ##############################
182
183#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
184; ---------------------------------------------
185; Level 2 ISR: Can interrupt a Level 1 ISR
186; ---------------------------------------------
187ENTRY(handle_interrupt_level2)
188
189 INTERRUPT_PROLOGUE 2
190
191 ;------------------------------------------------------
192 ; if L2 IRQ interrupted a L1 ISR, disable preemption
193 ;------------------------------------------------------
194
195 ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
196 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
197
198 ; A1 is set in status32_l2
199 ; bump thread_info->preempt_count (Disable preemption)
200 GET_CURR_THR_INFO_FROM_SP r10
201 ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
202 add r9, r9, 1
203 st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
204
2051:
206 ;------------------------------------------------------
207 ; setup params for Linux common ISR and invoke it
208 ;------------------------------------------------------
209 lr r0, [icause2]
210 and r0, r0, 0x1f
211
212 bl.d @arch_do_IRQ
213 mov r1, sp
214
215 mov r8,0x2
216 sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
217
218 b ret_from_exception
219
220END(handle_interrupt_level2)
221
222#endif
223
224; ---------------------------------------------
225; Level 1 ISR
226; ---------------------------------------------
227ENTRY(handle_interrupt_level1)
228
229 INTERRUPT_PROLOGUE 1
230
231 lr r0, [icause1]
232 and r0, r0, 0x1f
233
234#ifdef CONFIG_TRACE_IRQFLAGS
235 ; icause1 needs to be read early, before calling tracing, which
236 ; can clobber scratch regs, hence use of stack to stash it
237 push r0
238 TRACE_ASM_IRQ_DISABLE
239 pop r0
240#endif
241
242 bl.d @arch_do_IRQ
243 mov r1, sp
244
245 mov r8,0x1
246 sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
247
248 b ret_from_exception
249END(handle_interrupt_level1)
250
251;################### Non TLB Exception Handling #############################
252
253; ---------------------------------------------
254; Instruction Error Exception Handler
255; ---------------------------------------------
256
257ENTRY(instr_service)
258

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310 GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
311 st sp, [r10, THREAD_CALLEE_REG]
312
313 j do_machine_check_fault
314
315END(EV_MachineCheck)
316
317; ---------------------------------------------
27;################### Non TLB Exception Handling #############################
28
29; ---------------------------------------------
30; Instruction Error Exception Handler
31; ---------------------------------------------
32
33ENTRY(instr_service)
34

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86 GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
87 st sp, [r10, THREAD_CALLEE_REG]
88
89 j do_machine_check_fault
90
91END(EV_MachineCheck)
92
93; ---------------------------------------------
318; Protection Violation Exception Handler
319; ---------------------------------------------
320
321ENTRY(EV_TLBProtV)
322
323 EXCEPTION_PROLOGUE
324
325 lr r2, [ecr]
326 lr r0, [efa] ; Faulting Data addr (not part of pt_regs saved above)
327
328 ; Exception auto-disables further Intr/exceptions.
329 ; Re-enable them by pretending to return from exception
330 ; (so rest of handler executes in pure K mode)
331
332 FAKE_RET_FROM_EXCPN
333
334 mov r1, sp ; Handle to pt_regs
335
336 ;------ (5) Type of Protection Violation? ----------
337 ;
338 ; ProtV Hardware Exception is triggered for Access Faults of 2 types
339 ; -Access Violaton : 00_23_(00|01|02|03)_00
340 ; x r w r+w
341 ; -Unaligned Access : 00_23_04_00
342 ;
343 bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f
344
345 ;========= (6a) Access Violation Processing ========
346 bl do_page_fault
347 b ret_from_exception
348
349 ;========== (6b) Non aligned access ============
3504:
351
352 SAVE_CALLEE_SAVED_USER
353 mov r2, sp ; callee_regs
354
355 bl do_misaligned_access
356
357 ; TBD: optimize - do this only if a callee reg was involved
358 ; either a dst of emulated LD/ST or src with address-writeback
359 RESTORE_CALLEE_SAVED_USER
360
361 b ret_from_exception
362
363END(EV_TLBProtV)
364
365; Wrapper for Linux page fault handler called from EV_TLBMiss*
366; Very similar to ProtV handler case (6a) above, but avoids the extra checks
367; for Misaligned access
368;
369ENTRY(call_do_page_fault)
370
371 EXCEPTION_PROLOGUE
372 lr r0, [efa] ; Faulting Data address
373 mov r1, sp
374 FAKE_RET_FROM_EXCPN
375
376 mov blink, ret_from_exception
377 b do_page_fault
378
379END(call_do_page_fault)
380
381; ---------------------------------------------
382; Privilege Violation Exception Handler
383; ---------------------------------------------
384ENTRY(EV_PrivilegeV)
385
386 EXCEPTION_PROLOGUE
387
388 lr r0, [efa]
389 mov r1, sp

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620 bbit0 r9, TIF_NEED_RESCHED, .Lrestore_regs
621
622 ; Invoke PREEMPTION
623 bl preempt_schedule_irq
624
625 ; preempt_schedule_irq() always returns with IRQ disabled
626#endif
627
94; Privilege Violation Exception Handler
95; ---------------------------------------------
96ENTRY(EV_PrivilegeV)
97
98 EXCEPTION_PROLOGUE
99
100 lr r0, [efa]
101 mov r1, sp

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332 bbit0 r9, TIF_NEED_RESCHED, .Lrestore_regs
333
334 ; Invoke PREEMPTION
335 bl preempt_schedule_irq
336
337 ; preempt_schedule_irq() always returns with IRQ disabled
338#endif
339
628 ; fall through
629
630;############# Return from Intr/Excp/Trap (ARC Specifics) ##############
631;
632; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
633; IRQ shd definitely not happen between now and rtie
634; All 2 entry points to here already disable interrupts
635
636.Lrestore_regs:
637
638 TRACE_ASM_IRQ_ENABLE
639
640 lr r10, [status32]
641
642 ; Restore REG File. In case multiple Events outstanding,
643 ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
644 ; Note that we use realtime STATUS32 (not pt_regs->status32) to
645 ; decide that.
646
647 ; if Returning from Exception
648 bbit0 r10, STATUS_AE_BIT, not_exception
649 EXCEPTION_EPILOGUE
650 rtie
651
652 ; Not Exception so maybe Interrupts (Level 1 or 2)
653
654not_exception:
655
656#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
657
658 ; Level 2 interrupt return Path - from hardware standpoint
659 bbit0 r10, STATUS_A2_BIT, not_level2_interrupt
660
661 ;------------------------------------------------------------------
662 ; However the context returning might not have taken L2 intr itself
663 ; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
664 ; Special considerations needed for the context which took L2 intr
665
666 ld r9, [sp, PT_event] ; Ensure this is L2 intr context
667 brne r9, event_IRQ2, 149f
668
669 ;------------------------------------------------------------------
670 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
671 ; so that sched doesn't move to new task, causing L1 to be delayed
672 ; undeterministically. Now that we've achieved that, let's reset
673 ; things to what they were, before returning from L2 context
674 ;----------------------------------------------------------------
675
676 ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
677 bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
678
679 ; decrement thread_info->preempt_count (re-enable preemption)
680 GET_CURR_THR_INFO_FROM_SP r10
681 ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
682
683 ; paranoid check, given A1 was active when A2 happened, preempt count
684 ; must not be 0 because we would have incremented it.
685 ; If this does happen we simply HALT as it means a BUG !!!
686 cmp r9, 0
687 bnz 2f
688 flag 1
689
6902:
691 sub r9, r9, 1
692 st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
693
694149:
695 ;return from level 2
696 INTERRUPT_EPILOGUE 2
697debug_marker_l2:
698 rtie
699
700not_level2_interrupt:
701
702#endif
703
704 bbit0 r10, STATUS_A1_BIT, not_level1_interrupt
705
706 ;return from level 1
707 INTERRUPT_EPILOGUE 1
708debug_marker_l1:
709 rtie
710
711not_level1_interrupt:
712
713 ;this case is for syscalls or Exceptions (with fake rtie)
714
715 EXCEPTION_EPILOGUE
716debug_marker_syscall:
717 rtie
718
340 b .Lrestore_regs
719END(ret_from_exception)
720
721ENTRY(ret_from_fork)
722 ; when the forked child comes here from the __switch_to function
723 ; r0 has the last task pointer.
724 ; put last task in scheduler queue
725 bl @schedule_tail
726

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757
758#ifdef CONFIG_ARC_DW2_UNWIND
759; Workaround for bug 94179 (STAR ):
760; Despite -fasynchronous-unwind-tables, linker is not making dwarf2 unwinder
761; section (.debug_frame) as loadable. So we force it here.
762; This also fixes STAR 9000487933 where the prev-workaround (objcopy --setflag)
763; would not work after a clean build due to kernel build system dependencies.
764.section .debug_frame, "wa",@progbits
341END(ret_from_exception)
342
343ENTRY(ret_from_fork)
344 ; when the forked child comes here from the __switch_to function
345 ; r0 has the last task pointer.
346 ; put last task in scheduler queue
347 bl @schedule_tail
348

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379
380#ifdef CONFIG_ARC_DW2_UNWIND
381; Workaround for bug 94179 (STAR ):
382; Despite -fasynchronous-unwind-tables, linker is not making dwarf2 unwinder
383; section (.debug_frame) as loadable. So we force it here.
384; This also fixes STAR 9000487933 where the prev-workaround (objcopy --setflag)
385; would not work after a clean build due to kernel build system dependencies.
386.section .debug_frame, "wa",@progbits
387
388; Reset to .text as this file is included in entry-<isa>.S
389.section .text, "ax",@progbits
765#endif
390#endif