mmu.h (a79a9c765f95a73e087f11f0994297cd69987bda) mmu.h (2cc1121bc993ca3090cc4267bc38d3da61b68602)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 */
5
6#ifndef _ASM_ARC_MMU_H
7#define _ASM_ARC_MMU_H
8
9#ifndef __ASSEMBLY__
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 */
5
6#ifndef _ASM_ARC_MMU_H
7#define _ASM_ARC_MMU_H
8
9#ifndef __ASSEMBLY__
10
10#include <linux/threads.h> /* NR_CPUS */
11#include <linux/threads.h> /* NR_CPUS */
11#endif
12
12
13/* MMU Management regs */
14#define ARC_REG_MMU_BCR 0x06f
15
16#ifdef CONFIG_ARC_MMU_V3
17#define ARC_REG_TLBPD0 0x405
18#define ARC_REG_TLBPD1 0x406
19#define ARC_REG_TLBPD1HI 0 /* Dummy: allows code sharing with ARC700 */
20#define ARC_REG_TLBINDEX 0x407
21#define ARC_REG_TLBCOMMAND 0x408
22#define ARC_REG_PID 0x409
23#define ARC_REG_SCRATCH_DATA0 0x418
24#else
25#define ARC_REG_TLBPD0 0x460
26#define ARC_REG_TLBPD1 0x461
27#define ARC_REG_TLBPD1HI 0x463
28#define ARC_REG_TLBINDEX 0x464
29#define ARC_REG_TLBCOMMAND 0x465
30#define ARC_REG_PID 0x468
31#define ARC_REG_SCRATCH_DATA0 0x46c
32#endif
33
34/* Bits in MMU PID register */
35#define __TLB_ENABLE (1 << 31)
36#define __PROG_ENABLE (1 << 30)
37#define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE)
38
39/* Error code if probe fails */
40#define TLB_LKUP_ERR 0x80000000
41
42#ifdef CONFIG_ARC_MMU_V3
43#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001)
44#else
45#define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000)
46#endif
47
48/* TLB Commands */
49#define TLBWrite 0x1
50#define TLBRead 0x2
51#define TLBGetIndex 0x3
52#define TLBProbe 0x4
53#define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */
54#define TLBIVUTLB 0x6 /* explicitly inv uTLBs */
55
56#ifdef CONFIG_ARC_MMU_V4
57#define TLBInsertEntry 0x7
58#define TLBDeleteEntry 0x8
59#endif
60
61#ifndef __ASSEMBLY__
62
63typedef struct {
64 unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */
65} mm_context_t;
66
13typedef struct {
14 unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */
15} mm_context_t;
16
67static inline void mmu_setup_asid(struct mm_struct *mm, unsigned int asid)
68{
69 write_aux_reg(ARC_REG_PID, asid | MMU_ENABLE);
70}
71
72static inline void mmu_setup_pgd(struct mm_struct *mm, void *pgd)
73{
74 /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */
75#ifdef CONFIG_ISA_ARCV2
76 write_aux_reg(ARC_REG_SCRATCH_DATA0, (unsigned int)pgd);
77#endif
17#endif
78}
79
18
80static inline int is_pae40_enabled(void)
81{
82 return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
83}
19#include <asm/mmu-arcv2.h>
84
20
85extern int pae40_exist_but_not_enab(void);
86
87#else
88
89.macro ARC_MMU_REENABLE reg
90 lr \reg, [ARC_REG_PID]
91 or \reg, \reg, MMU_ENABLE
92 sr \reg, [ARC_REG_PID]
93.endm
94
95#endif /* !__ASSEMBLY__ */
96
97#endif
21#endif