| xillybus.rst (0898782247ae533d1f4e47a06bc5d4870931b284) | xillybus.rst (f31a03b123b1f849bc0f60493edb95342f2c8e9a) |
|---|---|
| 1========================================== 2Xillybus driver for generic FPGA interface 3========================================== 4 5:Author: Eli Billauer, Xillybus Ltd. (http://xillybus.com) 6:Email: eli.billauer@gmail.com or as advertised on Xillybus' site. 7 8.. Contents: --- 259 unchanged lines hidden (view full) --- 268sides, the implementation relies on a set of DMA buffers which is allocated 269for each channel. For the sake of illustration, let's take the FPGA to host 270direction: As data streams into the respective channel's interface in the 271FPGA, the Xillybus IP core writes it to one of the DMA buffers. When the 272buffer is full, the FPGA informs the host about that (appending a 273XILLYMSG_OPCODE_RELEASEBUF message channel 0 and sending an interrupt if 274necessary). The host responds by making the data available for reading through 275the character device. When all data has been read, the host writes on the | 1========================================== 2Xillybus driver for generic FPGA interface 3========================================== 4 5:Author: Eli Billauer, Xillybus Ltd. (http://xillybus.com) 6:Email: eli.billauer@gmail.com or as advertised on Xillybus' site. 7 8.. Contents: --- 259 unchanged lines hidden (view full) --- 268sides, the implementation relies on a set of DMA buffers which is allocated 269for each channel. For the sake of illustration, let's take the FPGA to host 270direction: As data streams into the respective channel's interface in the 271FPGA, the Xillybus IP core writes it to one of the DMA buffers. When the 272buffer is full, the FPGA informs the host about that (appending a 273XILLYMSG_OPCODE_RELEASEBUF message channel 0 and sending an interrupt if 274necessary). The host responds by making the data available for reading through 275the character device. When all data has been read, the host writes on the |
| 276the FPGA's buffer control register, allowing the buffer's overwriting. Flow | 276FPGA's buffer control register, allowing the buffer's overwriting. Flow |
| 277control mechanisms exist on both sides to prevent underflows and overflows. 278 279This is not good enough for creating a TCP/IP-like stream: If the data flow 280stops momentarily before a DMA buffer is filled, the intuitive expectation is 281that the partial data in buffer will arrive anyhow, despite the buffer not 282being completed. This is implemented by adding a field in the 283XILLYMSG_OPCODE_RELEASEBUF message, through which the FPGA informs not just 284which buffer is submitted, but how much data it contains. --- 95 unchanged lines hidden --- | 277control mechanisms exist on both sides to prevent underflows and overflows. 278 279This is not good enough for creating a TCP/IP-like stream: If the data flow 280stops momentarily before a DMA buffer is filled, the intuitive expectation is 281that the partial data in buffer will arrive anyhow, despite the buffer not 282being completed. This is implemented by adding a field in the 283XILLYMSG_OPCODE_RELEASEBUF message, through which the FPGA informs not just 284which buffer is submitted, but how much data it contains. --- 95 unchanged lines hidden --- |