edac.rst (6634fbb6b6356e6f5b428a349952b368b25d514d) edac.rst (6b1fb6f7037221981fb2cf1822c31b5fba1b9c22)
1Error Detection And Correction (EDAC) Devices
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3
1Error Detection And Correction (EDAC) Devices
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3
4Main Concepts used at the EDAC subsystem
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6
7There are several things to be aware of that aren't at all obvious, like
8*sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
9etc...
10
11These are some of the many terms that are thrown about that don't always
12mean what people think they mean (Inconceivable!). In the interest of
13creating a common ground for discussion, terms and their definitions
14will be established.
15
16* Memory devices
17
18The individual DRAM chips on a memory stick. These devices commonly
19output 4 and 8 bits each (x4, x8). Grouping several of these in parallel
20provides the number of bits that the memory controller expects:
21typically 72 bits, in order to provide 64 bits + 8 bits of ECC data.
22
23* Memory Stick
24
25A printed circuit board that aggregates multiple memory devices in
26parallel. In general, this is the Field Replaceable Unit (FRU) which
27gets replaced, in the case of excessive errors. Most often it is also
28called DIMM (Dual Inline Memory Module).
29
30* Memory Socket
31
32A physical connector on the motherboard that accepts a single memory
33stick. Also called as "slot" on several datasheets.
34
35* Channel
36
37A memory controller channel, responsible to communicate with a group of
38DIMMs. Each channel has its own independent control (command) and data
39bus, and can be used independently or grouped with other channels.
40
41* Branch
42
43It is typically the highest hierarchy on a Fully-Buffered DIMM memory
44controller. Typically, it contains two channels. Two channels at the
45same branch can be used in single mode or in lockstep mode. When
46lockstep is enabled, the cacheline is doubled, but it generally brings
47some performance penalty. Also, it is generally not possible to point to
48just one memory stick when an error occurs, as the error correction code
49is calculated using two DIMMs instead of one. Due to that, it is capable
50of correcting more errors than on single mode.
51
52* Single-channel
53
54The data accessed by the memory controller is contained into one dimm
55only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
56one 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3
57memories. FB-DIMM and RAMBUS use a different concept for channel, so
58this concept doesn't apply there.
59
60* Double-channel
61
62The data size accessed by the memory controller is interlaced into two
63dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
64bits with ECC), the data flows to the CPU using a 128 bits parallel
65access.
66
67* Chip-select row
68
69This is the name of the DRAM signal used to select the DRAM ranks to be
70accessed. Common chip-select rows for single channel are 64 bits, for
71dual channel 128 bits. It may not be visible by the memory controller,
72as some DIMM types have a memory buffer that can hide direct access to
73it from the Memory Controller.
74
75* Single-Ranked stick
76
77A Single-ranked stick has 1 chip-select row of memory. Motherboards
78commonly drive two chip-select pins to a memory stick. A single-ranked
79stick, will occupy only one of those rows. The other will be unused.
80
81.. _doubleranked:
82
83* Double-Ranked stick
84
85A double-ranked stick has two chip-select rows which access different
86sets of memory devices. The two rows cannot be accessed concurrently.
87
88* Double-sided stick
89
90**DEPRECATED TERM**, see :ref:`Double-Ranked stick <doubleranked>`.
91
92A double-sided stick has two chip-select rows which access different sets
93of memory devices. The two rows cannot be accessed concurrently.
94"Double-sided" is irrespective of the memory devices being mounted on
95both sides of the memory stick.
96
97* Socket set
98
99All of the memory sticks that are required for a single memory access or
100all of the memory sticks spanned by a chip-select row. A single socket
101set has two chip-select rows and if double-sided sticks are used these
102will occupy those chip-select rows.
103
104* Bank
105
106This term is avoided because it is unclear when needing to distinguish
107between chip-select rows and socket sets.
108
109
4Memory Controllers
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6
7Most of the EDAC core is focused on doing Memory Controller error detection.
8The :c:func:`edac_mc_alloc`. It uses internally the struct ``mem_ctl_info``
9to describe the memory controllers, with is an opaque struct for the EDAC
10drivers. Only the EDAC core is allowed to touch it.
11

--- 61 unchanged lines hidden --- 		110Memory Controllers
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112
113Most of the EDAC core is focused on doing Memory Controller error detection.
114The :c:func:`edac_mc_alloc`. It uses internally the struct ``mem_ctl_info``
115to describe the memory controllers, with is an opaque struct for the EDAC
116drivers. Only the EDAC core is allowed to touch it.
117

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