| booting.rst (e4624435f38b34e7ce827070aa0f8b533a37c07e) | booting.rst (6aeadf7896bff4ca230702daba8788455e6b866e) |
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| 1===================== 2Booting AArch64 Linux 3===================== 4 5Author: Will Deacon <will.deacon@arm.com> 6 7Date : 07 September 2012 8 --- 365 unchanged lines hidden (view full) --- 374 - If EL3 is present: 375 376 - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1. 377 378 - If the kernel is entered at EL1 and EL2 is present: 379 380 - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1. 381 | 1===================== 2Booting AArch64 Linux 3===================== 4 5Author: Will Deacon <will.deacon@arm.com> 6 7Date : 07 September 2012 8 --- 365 unchanged lines hidden (view full) --- 374 - If EL3 is present: 375 376 - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1. 377 378 - If the kernel is entered at EL1 and EL2 is present: 379 380 - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1. 381 |
| 382 For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS): 383 384 - If the kernel is entered at EL1 and EL2 is present: 385 386 - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1. 387 388 For CPUs with the Extended Translation Control Register feature (FEAT_TCR2): 389 390 - If EL3 is present: 391 392 - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1. 393 394 - If the kernel is entered at EL1 and EL2 is present: 395 396 - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1. 397 398 For CPUs with the Stage 1 Permission Indirection Extension feature (FEAT_S1PIE): 399 400 - If EL3 is present: 401 402 - SCR_EL3.PIEn (bit 45) must be initialised to 0b1. 403 404 - If the kernel is entered at EL1 and EL2 is present: 405 406 - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1. 407 408 - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1. 409 410 - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1. 411 412 - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1. 413 |
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| 382The requirements described above for CPU mode, caches, MMUs, architected 383timers, coherency and system registers apply to all CPUs. All CPUs must 384enter the kernel in the same exception level. Where the values documented 385disable traps it is permissible for these traps to be enabled so long as 386those traps are handled transparently by higher exception levels as though 387the values documented were set. 388 389The boot loader is expected to enter the kernel on each CPU in the --- 42 unchanged lines hidden --- | 414The requirements described above for CPU mode, caches, MMUs, architected 415timers, coherency and system registers apply to all CPUs. All CPUs must 416enter the kernel in the same exception level. Where the values documented 417disable traps it is permissible for these traps to be enabled so long as 418those traps are handled transparently by higher exception levels as though 419the values documented were set. 420 421The boot loader is expected to enter the kernel on each CPU in the --- 42 unchanged lines hidden --- |