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Searched refs:zext (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/arch/csky/abiv2/
H A Dmemset.S28 zext r18, r2, 31, 4
43 zext r18, r2, 3, 2
54 zext r18, r2, 2, 0
H A Dmemcpy.S22 zext r18, r2, 31, 4
57 zext r18, r2, 3, 2
69 zext r18, r2, 1, 0
H A Dmemmove.S28 zext r18, r2, 31, 4
61 zext r18, r2, 3, 2
73 zext r18, r2, 1, 0
H A Dmemcmp.S24 zext r18, r2, 31, 4
58 zext r18, r2, 3, 2
71 zext r18, r2, 1, 0
/openbmc/linux/arch/loongarch/net/
H A Dbpf_jit.h119 goto zext; in move_imm()
125 goto zext; in move_imm()
165 zext: in move_imm()
/openbmc/linux/Documentation/bpf/
H A Dbpf_design_QA.rst180 is required, and insert an explicit zero-extension (zext) instruction
181 (a mov32 variant). This means that for architectures without zext hardware
186 enable zext insertion in the verifier).
189 support for zext. In that case, if verifier zext insertion is enabled,
190 it could lead to the insertion of unnecessary zext instructions. Such
192 back-end: if one instruction has hardware support for zext and if the next
193 instruction is an explicit zext, then the latter can be skipped when doing
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_xthead.c.inc88 * If zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2).
344 * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
364 * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
738 * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
755 * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2).
/openbmc/qemu/target/riscv/
H A Dinsn32.decode774 # The encoding for zext.h differs between RV32 and RV64.
807 # The encoding for zext.h differs between RV32 and RV64.
/openbmc/qemu/target/arm/tcg/
H A Dtranslate-a64.c7461 MemOp sign, bool zext) in do_scalar_shift_imm_narrow() argument
7473 if (zext) { in do_scalar_shift_imm_narrow()