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Searched refs:wvmcs (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/target/i386/hvf/
H A Dvmx.h96 wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer); in enter_long_mode()
103 wvmcs(vcpu, VMCS_GUEST_TR_ACCESS_RIGHTS, in enter_long_mode()
116 wvmcs(vcpu, VMCS_GUEST_IA32_EFER, efer); in exit_long_mode()
141 wvmcs(vcpu, VMCS_CR0_MASK, mask); in macvm_set_cr0()
142 wvmcs(vcpu, VMCS_CR0_SHADOW, cr0); in macvm_set_cr0()
168 wvmcs(vcpu, VMCS_GUEST_CR4, guest_cr4); in macvm_set_cr4()
169 wvmcs(vcpu, VMCS_CR4_SHADOW, cr4); in macvm_set_cr4()
170 wvmcs(vcpu, VMCS_CR4_MASK, CR4_VMXE_MASK); in macvm_set_cr4()
190 wvmcs(cpu->accel->fd, VMCS_GUEST_INTERRUPTIBILITY, in macvm_set_rip()
222 wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val | in vmx_set_nmi_window_exiting()
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H A Dx86_descr.c72 wvmcs(cpu->accel->fd, vmx_segment_fields[seg].selector, selector.sel); in vmx_write_segment_selector()
87 wvmcs(cpu->accel->fd, sf->base, desc->base); in vmx_write_segment_descriptor()
88 wvmcs(cpu->accel->fd, sf->limit, desc->limit); in vmx_write_segment_descriptor()
89 wvmcs(cpu->accel->fd, sf->selector, desc->sel); in vmx_write_segment_descriptor()
90 wvmcs(cpu->accel->fd, sf->ar_bytes, desc->ar); in vmx_write_segment_descriptor()
H A Dx86hvf.c90 wvmcs(cs->accel->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit); in hvf_put_segments()
91 wvmcs(cs->accel->fd, VMCS_GUEST_IDTR_BASE, env->idt.base); in hvf_put_segments()
93 wvmcs(cs->accel->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit); in hvf_put_segments()
94 wvmcs(cs->accel->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base); in hvf_put_segments()
97 wvmcs(cs->accel->fd, VMCS_GUEST_CR3, env->cr[3]); in hvf_put_segments()
99 wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, env->efer); in hvf_put_segments()
331 wvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val | in vmx_set_int_window_exiting()
339 wvmcs(cs->accel->fd, VMCS_PRI_PROC_BASED_CTLS, val & in vmx_clear_int_window_exiting()
394 wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, info); in hvf_inject_interrupts()
402 wvmcs(cs->accel->fd, VMCS_ENTRY_INTR_INFO, info); in hvf_inject_interrupts()
[all …]
H A Dhvf.c90 wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); in vmx_update_tpr()
92 wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : in vmx_update_tpr()
279 wvmcs(cpu->accel->fd, VMCS_PIN_BASED_CTLS, in hvf_arch_init_vcpu()
284 wvmcs(cpu->accel->fd, VMCS_PRI_PROC_BASED_CTLS, in hvf_arch_init_vcpu()
299 wvmcs(cpu->accel->fd, VMCS_SEC_PROC_BASED_CTLS, in hvf_arch_init_vcpu()
302 wvmcs(cpu->accel->fd, VMCS_ENTRY_CTLS, in hvf_arch_init_vcpu()
304 wvmcs(cpu->accel->fd, VMCS_EXCEPTION_BITMAP, 0); /* Double fault */ in hvf_arch_init_vcpu()
306 wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); in hvf_arch_init_vcpu()
H A Dx86_task.c64 wvmcs(cpu->accel->fd, VMCS_GUEST_CR3, tss->cr3); in load_state_from_tss32()
H A Dx86_emu.c781 wvmcs(cs->accel->fd, VMCS_GUEST_FS_BASE, data); in simulate_wrmsr()
784 wvmcs(cs->accel->fd, VMCS_GUEST_GS_BASE, data); in simulate_wrmsr()
787 wvmcs(cs->accel->fd, VMCS_HOST_FS_BASE, data); in simulate_wrmsr()
800 wvmcs(cs->accel->fd, VMCS_GUEST_IA32_EFER, data); in simulate_wrmsr()