Searched refs:vlv_dpio_read (Results 1 – 6 of 6) sorted by relevance
/openbmc/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_dpio_phy.c | 699 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level() 713 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level() 719 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_set_phy_signal_level() 790 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_data_lane_soft_reset() 806 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_data_lane_soft_reset() 854 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_phy_pre_pll_enable() 862 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_phy_pre_pll_enable() 872 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_phy_pre_pll_enable() 895 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_phy_pre_pll_enable() 1007 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_phy_post_pll_disable() [all …]
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H A D | intel_dpll.c | 1639 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp() 1644 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp() 1649 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp() 1653 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp() 1686 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); in vlv_prepare_pll() 1738 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); in vlv_prepare_pll() 1829 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); in chv_prepare_pll() 1837 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); in chv_prepare_pll() 1877 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | in chv_prepare_pll() 1894 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in _chv_enable_pll() [all …]
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H A D | intel_display_power_well.c | 1442 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); in chv_dpio_cmn_power_well_enable() 1448 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); in chv_dpio_cmn_power_well_enable() 1457 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); in chv_dpio_cmn_power_well_enable() 1532 val = vlv_dpio_read(dev_priv, pipe, reg); in assert_chv_phy_powergate()
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H A D | intel_display.c | 2805 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); in vlv_crtc_clock_get() 2833 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); in chv_crtc_clock_get() 2834 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); in chv_crtc_clock_get() 2835 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); in chv_crtc_clock_get() 2836 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); in chv_crtc_clock_get() 2837 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); in chv_crtc_clock_get()
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/openbmc/linux/drivers/gpu/drm/i915/ |
H A D | vlv_sideband.h | 78 u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
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H A D | vlv_sideband.c | 230 u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg) in vlv_dpio_read() function
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